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I am using hardware with an 8 MHz external crystal and would like to reduce the SYSCLK frequency to 1MHz. I haven't been able to do this yet. Is it possible to achieve this with certain PLL and DIV settings?

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  • \$\begingroup\$ What's the importance of a 1 MHz SYSCLK? \$\endgroup\$ – Colin Apr 13 '18 at 13:07
  • \$\begingroup\$ He means probably the core clock \$\endgroup\$ – P__J__ Apr 13 '18 at 13:28
  • \$\begingroup\$ @Colin__s OP's lost interest. \$\endgroup\$ – P__J__ Apr 13 '18 at 21:26
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Nope, according to the datasheet the output from the PLL must be between 16 and 48 MHz and there's no way to put an external crystal through a divider before reaching the sysclk (see the clock tree on page 14 of the datasheet).

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  • \$\begingroup\$ Can the downvoter please say what's wrong with this answer? \$\endgroup\$ – Colin Apr 13 '18 at 13:38
  • \$\begingroup\$ Not sure either. Answer looks correct to me. Have an up vote. \$\endgroup\$ – Jon Apr 13 '18 at 13:48
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Of course it is possible.

Here is the configuration for F031c6

enter image description here

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    \$\begingroup\$ This is wrong. The OP asks for a 1MHz SYSCLK, your picture shows a 16MHz SYSCLK. \$\endgroup\$ – Colin Apr 13 '18 at 13:36
  • \$\begingroup\$ I bet he means the core clock \$\endgroup\$ – P__J__ Apr 13 '18 at 14:51

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