First lets look at the error message.
Error (10170): Verilog HDL syntax error at transmitter.v (4) near text "reg"; expecting an identifier ("reg" is a reserved keyword ), or "[", or "signed", or "unsigned"
On or near line 4 there is an error - near to a bit of text that reads "reg".
On line 4 we have
wire reg [7:0] PD; - I spot the text "reg".
After the wire keyword, you must either give an identifier (the name of a wire), or a
[ (in case of a multi-bit wire), or specify whether the wire is
unsigned (default). Instead you have used a reserved keyword
You can't have a signal that is both a wire and a reg.
Next, assuming you intend
PD to be a
reg, the line
assign PD[7:0]= PDin[7:0]; is also an error - you can't assign a reg using an assign statement. If you intended
PD to be a
wire, then you can't use it in the
always block later on.
I didn't use
Yes you did, you used it as the target of both a procedural assignment, and a continuous assignment. So you did use it. And in a way that is not allowed (see above).
As a third point, for readability, all of your
always statements should have a
begin and an
end keyword. You use
end in the same way you would use
} in C. It might seem tedious, but it is good practice and will save you time in the long run.
As a final point, if you want to perform some action (e.g. sending data bits) on and event (e.g. a signal going high), you should look into building a state machine to control the flow. Remember that everything you are describing with Verilog is hardware (hence HDL), so if you want to perform a sequence of actions, you need a hardware construct which does that - a state machine is one example.