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I'm not asking about manufacturing. I'm asking about designing electronics to survive normal use in the field. I want to figure out just how necessary it is to include TVS diodes in my design.

As I mentioned in my previous question, rarely did anyone bother in the 80s and 90s to include any ESD protection on I/O lines. These devices seem to survive OK.

I imagine it will depend on what type of ICs the I/O lines are connected to. In the 80s and 90s, they were generally NMOS VLSIs, early CMOS VLSIs, CMOS and TTL gates.

Are modern 5V MCUs more vulnerable than 74HC gates, warranting the inclusion of TVS diodes on the I/O pins?

Does the type of connector dictate the degree of ESD protection required? I can see a female D-sub connector being reasonably safe without any ESD protection - unless the cable itself is charged.

If I do need TVS diodes, then do I also need series resistors? I looked at the datasheet for a suitable 5V TVS, it specifies a maximum voltage drop of 24V when shunting a 20 amp ESD spike. If I connect the TVS directly to the I/O pin, the ESD diode inside the IC will conduct. 24V is much greater than the 0.3V ESD diode drop.

I could put a 33 ohm series resistor between the TVS and the I/O pin. This limits the current to less than an amp through the internal ESD diode which it can probably withstand. But is it really necessary? I have a lot of I/O pins and I'd rather avoid the resistor. Can I rely on the ESD diode having a sufficiently high dynamic resistance that the TVS will take the bulk of the discharge?

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ You should include ESD protection on anything that someone could touch after rubbing a balloon on their hair. \$\endgroup\$ – τεκ Apr 14 '18 at 0:00
  • \$\begingroup\$ You puzzle over something us design engineers accept as part of the assembly. Resistor on the inputs work great for IC's with built in clamp diodes, else add zeners or TVS to help. They are more likely to have static damage before assembly by those careless/untrained with ESD procedures. \$\endgroup\$ – Sparky256 Apr 14 '18 at 0:06
  • \$\begingroup\$ Foxie you clearly have no field experience. I used to blow even TTL with ESD in the 70's and CMOS latchup on long IO cables was always expected unless protected. Even if it still works is no guarantee you have not wounded it with partially bridged silicon. and higher junction capacitance. \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 '18 at 0:44
  • \$\begingroup\$ I'm aware that TTL is ESD sensitive, but it seems that most consumer designs of the 80s and even 90s barely bothered with any protection. I've done a fair bit of repair work, but it seems to be relatively uncommon to find a failed buffer on I/O ports. The only explanation I can think of is that connector design is protecting those pins. As for using resistors to protect pins, I was told this doesn't always work because the resistor may break down internally when subjected to tens of kV. \$\endgroup\$ – Foxie Apr 14 '18 at 1:38
  • \$\begingroup\$ Not every unit that fails is exposed to 5~15kV ESD stress but impulse voltages have sometimes 4 x the impulse breakdown threshold vs DC depending on capacitance , ESR , ionization time. But given neoprene soles and a nylon carpet, I'm sure I could break most units not designed for this stress. Ionization times tend to raise the withstanding threshold for passives depending on surface contaminants. ~x4 if ionically clean for sub-microsecond pulses \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 '18 at 3:13
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I counted at least five questions in your question. I will try to answer only few.

To begin, there are several levels of ESD events that can be specified by OEM of equipment, for different environment and other operating conditions, all classified in IEC 61000-4-2 standard.

Then yes, connector design does play a significant role in failure rate of electronic equipment. If a connector has a properly routed shield, and signal pins are recessed inside, there is much less chance that the signals will be exposed to direct ESD event, so they might require less level of ESD protection.

Second, TVS diodes do help even if they have clipping voltage of 20-25 V. This is still quite less than the 4 kV discharge from a normal human-body event, so it is quite easier to handle by internal protection.

And yes, in the 80s the feature size of silicon elements of transistors was 2000 nm, today it is much smaller, 1/100 of that, which makes them way more vulnerable to the same ESD energy. And no, there are no modern "5V" MCU, modern MCU are "1V" MCUs. The "5-V tolerant MCU are the blast from the past. There might be "5V" tolerant MCU, but either their functionality is not up to modern IoT demands, or you need to pay a premium for them.

The rest of questions are insignificant details.

In short, you likely want your product to survive in consumer or industrial environment and don't want to deal with product replacement and associated cost and risking to go out of business. You need to decide, is your business necessary for you? If yes, you don't ask questions and better use all accumulated engineering wisdom to protect your design from ESD.

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  • \$\begingroup\$ Yes if pure Silicon can withstand 30kV/mm or 30V/um and the junction capacitance is reduced from 30 to 1~3pF, then smaller gaps, the sensitivity to failure is increased for transients faster than the output protection diodes can respond for very short gap rise times in the 10~100ps range \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 '18 at 0:53
  • \$\begingroup\$ Thanks, so it looks like I can omit the series resistor? My impression is that the ESD diode being so small would tend to mean the bulk of the current gets shunted via the TVS anyway. \$\endgroup\$ – Foxie Apr 14 '18 at 1:40
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    \$\begingroup\$ @Foxie, this is not about any impression or other subtle feeling. This is about to design in a footprint for ESD protection, usually with several options, and test your product in a standard zapping table in accord with IEC 61000-4-2 specifications to the level required by your customer and their work environment. If it passes with a great margin, you can remove resistors and test again. etc. \$\endgroup\$ – Ale..chenski Apr 14 '18 at 7:23
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Robustness is a design choice you make.

Is you compare a small PIC/74HC vs the SOC in a raspberry pi or

PIC or other small 5V micro or 74HC logic: - small number of pins - plenty of room for wide metal tracks - high current pins 50mA capable = large fet area - true CMOS protection circuit - offloads static to the power supply with only diode drop - big pads+big transistors = big protection diodes = big fail current - basic cmos process used will be 3.3 or 5V

SOC / super-micro/fpga - Bazillion pins zigzagged bond pads, fine metalisation to thread between them - small fets, low current capability. Must be like this as it has so many pins - ?V tolerant input - protected by a zener arrangement: static is dissipated in the protection diode itself, not offloaded to supply rails - tiny bond pads and fets = tiny protection structure = tiny fail energy. - low voltage basic process 1.5V -2.5V

schematic

simulate this circuit – Schematic created using CircuitLab

So in summary:

Hi-tech parts: 7x dissipation in 1/10th the pad/transistor/metalisation area, in a cmos process 2x more voltage sensitve = 140x less robust. [flame war begins in carpark when bar closes]

Yes there is a big difference in the need for protection. But there are big differences in robustness, and they should be deliberate choices.

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You can avoid the repetition of many TVS diodes for each I/O line by using lower cost diodes like BAT54S to attach to the signal line. The catode of the upper diode connects to a common TVS that can be shared by multiple I/Os. The common anode/cathode connection goes to the signal line. Finally the lower diode anode goes to GND.

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Do you really need 33 ohm output impedance on your I/O? Because if you don't you can just put 10k and avoid latch up currents while letting internal ESD diodes do the work.

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  • Faraday discovered that the resistance of an ionzation arc was inverse with the current density. I read this in Maxwell's book A Treatise on Electricity and Magnetism an eBooK.pdf

ESD protection is not trivial. So learn as much as you can and follow best practices.

Thus the impedance of the Human Body Model (HMB) 100pF and the Cart model of 300pF have significantly different impedances in a discharge event not just because of C, but because of the unstated interface current density, actually varies dependent on the E field at the point of contact. A smooth surface has about 3x higher dielectric insulation to breakdown than a sharp point and thus as the gap can be smaller the current has less spreading effect and is a higher current , higher density and much faster rise time and thus much higher bandwidth. (RC=T=0.35/f). Discharges in dielectrics in large oil filled transformers can exceed >>10GHz and also include the optical spectrum.

ESD currents thus are variable but the test model source energy is fixed as defined by C and V but the power level depends on how short the pulse duration becomes.

We also know diode capacitance is inverse with the power capacity and ESR of the diode. Due to construction differences, we know TVS have the best (figure of merit (FOM)for zener like qualities and tiny Schottky diodes with two stages for ESR*C=T continue to be the best solution for CMOS internal protection tradeoffs between maximum speed and maximum protection. After all the diodes must respond fast than the CMOS latchup in order to protect them, but the size thus limits these diodes to 5 to 10mA max DC current from a DC power dissipation Absolute maximum.

So how is it that two stages is better and for greater protection adding TVS can improve this?

Intuition and simple transfer functions tell us the large series/shunt impedance ratio of any applied voltage can be attenuation greater than having a low series impedance.

schematic

simulate this circuit – Schematic created using CircuitLab

Advice

If you want to improve protection significantly with a series R or a ferrite bead, so long as that does not degrade your desired bandwidth from L/R or 1/RC = 0.35/f. A small bead is like 100pF shunt but it raises the rise time to allows the shunt diodes to respond faster than the input rise time.

I do not have enough time to devote to recent research and distill it down to one page, but there is ongoing research as CMOS lithography continues to shrink.

• new diode string structure has been developed for 65-nm ESD protection. • It possesses a 30% lower clamping voltage, a 15% lower overshoot voltage under very fast ESD pulse REF

enter image description here

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