# Why is D2 switched off and T4 not in saturation mode in 7408 TTL Gate as shown below? In the circuit, when both the inputs are high at 5V, than why is D2 switched off? Will it not draw voltage from Vcc?

Also, when one of the input is low, why is T4 not running in saturation mode? Will it not get high base current from Vcc?

Let me draw out the schematic using the editor (you should have done this, too.) simulate this circuit – Schematic created using CircuitLab

Here is a specification sheet for TTL: So the $A$ and $B$ inputs must be at least $2\:\text{V}$ each in your scenario. There is a reason for that. It guarantees that the emitters will be at least a diode drop above the voltage at the node $V_A$ shown in blue, above.

The reason is that the base-collector junction of $T_1$ will be forward-biased in this scenario, with current flowing through $R_B$, then via the base-collector junction of $T_1$, then via the base-emitter junction of $T_5$ and then via the base-emitter junction of $T_6$. So $V_A\approx 1.4\:\text{V}$, $V_B\approx 700\:\text{mV}$, and the base of $T_1$ will be approximately $2.1\:\text{V}$.

So if inputs $A$ and $B$ are both $\ge 2\:\text{V}$, the base-emitter junctions of $T_1$ will have no more than $100\:\text{mV}$ of forward biasing (which is effectively not at all) and will probably actually be reverse-biased in most practical cases. The TTL specification here is justified.

Since $V_A\approx 1.4\:\text{V}$ and $I_{R_\text{B}}=I_{\text{B}_{T_5}}=\frac{5\:\text{V}-2.1\:\text{V}}{4\:\text{k}\Omega}=725\:\mu\text{A}$, $T_5$ will be saturated with $V_{\text{CE}_5}\approx 200\:\text{mV}$ and therefore $V_C\approx 900\:\text{mV}$, give or take a little. $I_{R_4}=\frac{5\:\text{V}-900\:\text{mV}}{2\:\text{k}\Omega}\approx 2\:\text{mA}$.

Since $I_{R_5}=\frac{700\:\text{mV}}{800\:\Omega}\approx 900\:\mu\text{A}$, this leaves up to as much as $1.1\:\text{mA}$ as the base drive for $T_6$. $T_6$ will definitely be saturated and therefore $T_2$ is OFF.

Since $V_C\approx 900\:\text{mV}$ and since $V_{\text{CE}_6}\approx 200\:\text{mV}$, there will be approximately $700\:\text{mV}$ available to forward-bias $D_2$. While the exact details of how $I_{R_4}$ splits up between $D_2$ and the emitter of $T_5$ requires some difficult mathematics involving the LambertW function, it's sufficient to just realize that $T_6$ is saturated and $T_2$ is OFF. Because of that fact, $T_4$ is driven ON by $R_1$ and the output will be HI.

So to answer your first question, $D_2$ isn't necessarily off. It probably carries some current since it is forward-biased. But it doesn't matter how much because $T_6$'s collector is sinking all the current, regardless, and holding the base of $T_2$ close to ground.

Regarding your second question, once either of the inputs is pulled low enough ($\le 800\:\text{mV}$), then $T_1$'s base-emitter is forward-biased and therefore the base of $T_1$ will be $\le 1.5\:\text{V}$ and $I_{R_\text{B}}\ge \frac{5\:\text{V}-1.5\:\text{V}}{4\:\text{k}\Omega}$ meaning that the base current will be $\ge 875\:\mu\text{A}$ and will now saturate $T_5$, pulling its collector close to the emitter voltage. In this case, $V_A\le 800\:\text{mV}+200\:\text{mV}$, or $V_A\lt 1\:\text{V}$.

There is no current source to supply $T_5$'s base. But even if there were such a source, $V_B\lt 300\:\text{mV}$, and therefore $T_6$ is OFF (insufficiently biased to do much of anything.)

Now, $T_2$ is turned ON via current in $R_4$ and $D_2$, none of which is being sunk anymore by $T_6$'s collector (since it is OFF.)

With $T_2$ ON, the output will be LOW.

When both inputs are high, T5 is saturated ON allowing R4 current to bypass D2 and turn ON T6. This is a AND gate so if either input is LOW, then the above condition is false. T5/T6 is OFF and D2 acts as a bypass to turn on T2 and T3, thus a logic '0' output if any input is low.

This ties in with your second question. If any input is low then T2 and T3 are ON and T4 is OFF, as its base voltage is too low to turn ON.

If T6 is ON because both inputs are high then T2 and T3 are OFF, and T4 has full base voltage from R1 (T4 saturates) and outputs a logic '1'.