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This is a 555 timer circuit which is supposed to generate two short pulses, back to back, at a regular frequency. The top 555 is configured as astable to control the frequency. It feeds the first 555 to trigger the first pulse which in turn feeds the second to trigger the second pulse.

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The middle timer behaves as expected (green it output, blue is threshold, both from middle.

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However the output on the bottom timer never goes low when it triggers the threshold voltage (green is output, blue is threshold on bottom timer)

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Am I missing something, or is this a limitation of LTSpice?

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  • \$\begingroup\$ Did you modify the inverter's (A2) vhigh and vlow accordingly? The defaults are 1 and 0, but it looks like you need 5 and 0. Also, you don't need 3 separate supplies, just wire them to one. You may also want to add Rser (maybe Cpar, too) to the supply, to improve convergence (if there's a need for it). \$\endgroup\$
    – a concerned citizen
    Apr 14, 2018 at 19:01
  • \$\begingroup\$ When you build the circuit for real, you must add decoupling capacitors to each 555. also, the timing resistors are unusually low values. If you increase all four of them 10x, then the three timing capacitors reduce to 100 nF. This reduces stress on the Discharge transistor inside the 555. \$\endgroup\$
    – AnalogKid
    Jun 7, 2019 at 4:29

3 Answers 3

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The trigger input of a 555 is not inherently edge-sensitive, it's level- sensitive. If you want to trigger a timer on an edge, you need to AC-couple the signal using a high-pass filter that has a time constant significantly shorter than the timer period in question.

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To expand on Dave's answer, insert a 100 nF capacitor between U2 pin 3 and U3 pin 2. Add a 10 K pull up resistor between U3 pin 2 and Vcc. Because the Trigger input transition level is only 0.33 x Vcc, this is an approx. 0.28 ms pulse width, which is short enough not to interfere with U3's output timing.

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According to your question, the middle timer U2 operates as monostable multivibrator. It receives an active low trigger from U1.

Now, the output of U2 is +5.0V for a very short duration. Well, an inverter (NOT gate) is missing in its way till TRIGGER of U3. Therefore, in your case, the TRIGGER pin of U3 is always LOW but becomes HIGH only for a short duration.

So, a NOT gate should be connected between OUTPUT of U2 and TRIGGER of U3.

Hope this helps!

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  • \$\begingroup\$ This would cause both timers to trigger essentially simultaneously, rather than sequentially as the OP is asking for. \$\endgroup\$
    – Dave Tweed
    Apr 14, 2018 at 23:34
  • \$\begingroup\$ Yes, I agree with @DaveTweed \$\endgroup\$
    – user8908459
    Apr 15, 2018 at 4:53

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