# What is the use of pull-down networks in CMOS gates?

Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network.

What if we didn't put a NMOS in there? In low input voltages, we would have Vdd as expected but we would have ground voltage, which is zero, on output when we provide the network with high input voltage as well since p-channel mosfet would act like an open circuit hence blocking Vdd from reaching output cable. No, you wouldn't have ground voltage, you would have a floating or undefined voltage. This could cause havoc with the input to the next stage if it is a CMOS input. Its input impedance is so high that its input capacitance could hold it high when you switch off your arrangement. It would also be susceptible to stray electrical noise and switch randomly. simulate this circuit – Schematic created using CircuitLab

Figure 1. (a) Shows one gate driving another.

Figure 1a shows your gate driving a second one. Figure 1b shows a representation of your gate replaced with simple switches and driving the next gate.

All CMOS gates have some input capacitance. It's in their nature due to their construction. A capacitor tends to hold voltage across it unless there is some discharge path for it. The input impedance of CMOS gates is so high (GΩ) that discharge is very slow. Figure 1c represents your proposed scheme with only the P-channel switch. When SW5 is closed the input to the next stage is pulled high and that will work just fine. The problem occurs when SW5 is opened: C1 is charged and with no discharge path the input to the second gate (M11 and M12) will remain high.

This could be solved with the addition of R1 as shown in Figure 1d but now notice that when SW6 is closed that R1 is passing current all the time. This will waste power and CMOS is famous for its extremely low power consumption when not switching. (The power consumption rises with frequency as all the input capacitors have to be charged and discharged.)

For fast logic it is necessary to charge and discharge the next stage inputs as quickly as possible. The P-channel and N-channel arrangement of the standard gates achieve this very well.

• I am not sure if I really understand your answer. I am not majoring in EE so I am not familiar with the terms you are referring. I am sure your comment will help someone in future but I think I will wait for a simpler answer. Thanks for your precious effort.
– user183701
Apr 14, 2018 at 22:09
• Try the update. Apr 14, 2018 at 22:29

I will try to make as simple as I can

The pull down MOSTFET acts as a switch that connects the output line to ground which Is the zero voltage in your circuit.

When you remove the pull down MOSFET from the circuit and assuming the upper MOSFET is an open circuit the output line is now floating(Neither connected to ground Nor to Vdd) for most people this may be Okay since the output voltage is zero but Actually there is no voltage at all it just like a piece of wire connected to nothing but in The case where the pull down MOSFET is present the output is the zero reference Voltage.

Another important ability when you add the nmosfet is that the circuit can sink current You can thing of this as follows when output is High current goes form the upper MOSFET to the load so the circuit supplies the current

But when the output is LOW current goes into the circuit through the lower MOSFET to Ground

Now you have the current flowing in both direction from Vdd to the load when the Output is HIGH and from the load to ground when the output is LOW

This important feature won't be possible without the n-MOSFET

If you put LED (with resistor) to the output, it should shine or not depending on the input (and on where the LED is connected).

If you connect the LED between output and ground, it should shine, when the output is high (and input is low) and be dark otherwise - it works ok, with both current desing and your modification. (When the upper transistor is open, current goes from VCC via upper transistor, then LED to ground, LED shines. If the upper transistor is closed, no connection to VCC, LED does not shine.)

If you put LED between output and Vcc, it should shine, when the output is low (and input is high), and be dark otherwise.

If input is LOW, the upper transistor is open, the output is HIGH, LED is between VCC and HIGH, so no current can go, LED is dark - it is OK.

No for input HIGH (and so output LOW) - the LED shoud shine.

The current schema ensure it, as on HIGH input the low transistor is open, so current goes from VCC via LED and low transistor to ground - LED shines.

In your modification HIGH input close the upper transistor, but as there is no lower transistor. So current go from VCC via LED and there is no path to ground, so no current can go and LED is dark too - it fails.

What if we didn't put a NMOS in there?...
.. when we provide the network with high input voltage as well since p-channel mosfet would act like an open circuit hence blocking Vdd from reaching output cable.

Open p-MOS will make the output terminal floating. It won't give you 0 the required output.

Now what you can do to make it work as an inverter is to connect a resistor from output to ground. simulate this circuit – Schematic created using CircuitLab

In this circuit, current flow from Vdd to ground when p-MOS is ON. This problem of static power dissipation can be solved by using an n-MOS instead of resistor.

Using n-MOS ensures that only one MOSFET is ON at a time (except at transition) and hence no static power dissipation.