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I am using Quartus II 14.0 to perform this activity.

I have been trying to interface my CPU with an instruction memory module but I am not getting the correct response. The second instruction is not even recorded in my simulation waveforms. I don't see this problem when I produce simulation waveforms for my CPU alone. The following waveforms are my CPU waveforms.

enter image description here

As you can see, the program counter is incrementing properly and the instructions are also being recorded in the appropriate registers.

For my final lab however, I am required to connect this CPU with the instruction memory module. I have to specify this module as a mif file. I am aware of the fact that when creating this module via the Megawizard plug-in manager, many different files (.cmp, .vhd and .bsf) are created with it. The course coordinators however provide these files to us. I simply copied these files from the course directory and put them in my project directory. We were told not to make any changes to these files. I set the main simulation file (which was provided) as my top-level entity. My top-level file which I am not required to modify is as follows:

library ieee;
use ieee.std_logic_1164.all;

ENTITY CPU_TEST_Sim IS
    PORT
    (
        cpuClk              : in    std_logic;
        memClk              : in    std_logic;
        rst                 : in    std_logic;

        -- Debug data.
        outA, outB      : out   std_logic_vector(31 downto 0);
        outC, outZ          : out   std_logic;
        outIR                   : out   std_logic_vector(31 downto 0);
        outPC               : out   std_logic_vector(31 downto 0);

        -- Processor-Inst Memory Interface.
        addrOut             : out   std_logic_vector(5 downto 0);
        wEn                 : out   std_logic;
        memDataOut          : out   std_logic_vector(31 downto 0);
        memDataIn           : out   std_logic_vector(31 downto 0);

        -- Processor State
        T_Info              : out   std_logic_vector(2 downto 0);

        --data Memory Interface
        wen_mem, en_mem     : out std_logic);

END CPU_TEST_Sim;

ARCHITECTURE behavior OF CPU_TEST_Sim IS

    COMPONENT system_memory
        PORT
        (
            address     : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
            clock       : IN STD_LOGIC ;
            data        : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
            wren        : IN STD_LOGIC ;
            q           : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
        );
    END COMPONENT;

    COMPONENT cpu1
        PORT
        (       -- Input ports
            clk     : in    std_logic;
            mem_clk : in    std_logic;
            rst     : in    std_logic;
            dataIn  : in    std_logic_vector(31 downto 0);
            -- Output ports
            dataOut     : out   std_logic_vector(31 downto 0);
            addrOut     : out   std_logic_vector(31 downto 0);
            wEn             : out   std_logic;
            -- Debug data.
            dOutA, dOutB    : out   std_logic_vector(31 downto 0);
            dOutC, dOutZ    : out   std_logic;
            dOutIR          : out   std_logic_vector(31 downto 0);
            dOutPC          : out   std_logic_vector(31 downto 0);
            outT                : out   std_logic_vector(2 downto 0);
            wen_mem, en_mem : out std_logic);
    END COMPONENT;

    signal cpu_to_mem: std_logic_vector(31 downto 0);
    signal mem_to_cpu: std_logic_vector(31 downto 0);
    signal add_from_cpu: std_logic_vector(31 downto 0);
    signal wen_from_cpu: std_logic;

BEGIN

    -- Component instantiations.
    main_memory : system_memory
    PORT MAP
    (
        address => add_from_cpu(5 downto 0),
        clock => memClk,
        data => cpu_to_mem,
        wren => wen_from_cpu,
        q => mem_to_cpu
    );

    main_processor : cpu1
    PORT MAP
    (
        clk => cpuClk,
        mem_clk => memClk,
        rst => rst,
        dataIn => mem_to_cpu,
        dataOut => cpu_to_mem,
        addrOut => add_from_cpu,
        wEn => wen_from_cpu,
        dOutA => outA,
        dOutB => outB,
        dOutC => outC,
        dOutZ => outZ,
        dOutIR => outIR,
        dOutPC => outPC,
        outT => T_Info,
        wen_mem => wen_mem,
        en_mem => en_mem
    );

    addrOut <= add_from_cpu(5 downto 0);
    wEn <= wen_from_cpu;
    memDataOut <= mem_to_cpu;
    memDataIn <= cpu_to_mem;


END behavior;

I then right-clicked on system memory module, opened the plug-in manager and went through the steps in the order suggested in the manual.

enter image description here

enter image description here

After the step above I was warned that the files I have will get over-written and the .cmp file will also change. I allowed these files to get over-written and a .qip file was formed.

I specified fed two instructions into my mif file in the following way:

enter image description here

I am following the table in this document to specify the instructions.

However, as you can see in the following functional simulation waveform, none of the instructions after the first one are processed.

enter image description here

I have looked over the names very carefully and my port and signal assignments are correct. Why do you think this problem is then occurring? My program counter works properly in my standalone cpu file but does not when the instruction memory is involved. Is some error occurring when my mif file is being formed?

EDIT 1:

I get warnings when I compile my top-level entity file about inferred latches and unsafe behavior in my control path. I read that this is important when we are doing actual synthesis. I am only doing regular simulations here. Could it be causing problems for me?

EDIT 2:

I am getting these warnings. This link contains all the errors I am getting.

Warning (20028): Parallel compilation is not licensed and has been disabled Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "clr_IR", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ld_IR", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ld_PC", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "inc_PC", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "clr_A", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ld_A", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "clr_B", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ld_B", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "clr_C", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ld_C", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "clr_Z", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ld_Z", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "ALU_op", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "A_Mux", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ControlUnit.vhd(386): inferring latch(es) for signal or variable "B_Mux", which holds its previous value in one or more paths through ..........

EDIT 3:

My code for the control path

library ieee;
use ieee.std_logic_1164.ALL;

ENTITY ControlUnit IS
PORT(
    clk, mclk : IN STD_LOGIC;
    enable : IN STD_LOGIC;
    statusC, statusZ : IN STD_LOGIC;
    INST : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    A_Mux, B_Mux : OUT STD_LOGIC;
    IM_MUX1, REG_Mux : OUT STD_LOGIC;
    IM_MUX2, DATA_Mux : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    ALU_op : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    inc_PC, ld_PC : OUT STD_LOGIC;
    clr_IR : OUT STD_LOGIC;
    ld_IR : OUT STD_LOGIC;
    clr_A, clr_B, clr_C, clr_Z : OUT STD_LOGIC;
    ld_A, ld_B, ld_C, ld_Z : OUT STD_LOGIC;
    T : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    wen, en : OUT STD_LOGIC);
END ControlUnit;

ARCHITECTURE description OF ControlUnit IS
    TYPE STATETYPE IS (state_0, state_1, state_2);
    SIGNAL present_state: STATETYPE;
BEGIN
-------- OPERATION DECODER ---------
PROCESS (present_state, INST, statusC, statusZ, enable)
    BEGIN
-------- YOU FILL IN WHAT GOES IN HERE (DON'T FORGET TO CHECK FOR ENABLE)
-------- OUTPUT ASSIGNMENTS
                                    -- STATE T0
        IF (enable = '1') THEN
            IF (present_state = state_0) THEN --IR <= M[INST]
                clr_IR <= '0';
                ld_IR <= '1';
                ld_PC <= '0';
                inc_PC <= '0';
                clr_A <= '0';
                ld_A <= '0';
                clr_B <= '0';
                ld_B <= '0';
                clr_C <= '0';
                ld_C <= '0';
                clr_Z <= '0';
                ld_Z <= '0';
                ALU_op <= "000";
                A_Mux <= 'X';
                B_Mux <= 'X';
                REG_Mux <= 'X';
                DATA_Mux <= "00";
                IM_MUX1 <= '0';
                IM_MUX2 <= "00";
                                    -- STATE T1


                                                -- STATE T2
            ELSIF(present_state = state_1) THEN

            if (INST(31 DOWNTO 28)="0000") then --LDAI
                            clr_IR <= '0';
                            ld_IR <= '0';
                            --ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";
                            A_Mux <= '1';
                            REG_Mux <= 'X';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
    IM_MUX2 <= "00";
                            elsif (INST(31 DOWNTO 28)="0001") then
                    --LDBI
                            B_Mux <= '1';
                            clr_IR <= '0';
                            ld_IR <= '0';
                            --ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '1';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";
                            A_Mux <= '0';
                            B_Mux <= '1';
                            B_Mux <= '1';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                            elsif (INST(31 DOWNTO 28)="0010") then --STA
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';

                            clr_A <= '0';
                            ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";                            
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                            elsif (INST(31 DOWNTO 28)="0011") then --STB
                            clr_IR <= '0';
                            ld_IR <= '0';
                            --ld_PC <= '0';
                            clr_A <= '0';
ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";                            
                            A_Mux <= '0';
                            REG_Mux <= '1';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        end if;
                        inc_PC <= '1';
                        ld_PC <= '1';
            ELSIF(present_state = state_2) THEN
                B_Mux <= '1';
                inc_PC <= '0';
                CASE INST(31 DOWNTO 24) IS
                    WHEN "01110000" => --ADD
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
ALU_op <= "010";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01110001" => --ADDI
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "010";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "01";
                        WHEN "01110010" => --SUB
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
    ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "110";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01110011" => --INCA
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "010";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "10";
                        WHEN "01110100" => --ROL
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "100";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01110101" => --CLRA
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '1';
                            ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01110110" => --CLRB
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '0';
                            clr_B <= '1';
                            ld_B <= '0';
                            clr_C <= '0';
ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01110111" => --CLRC
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '1';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
WHEN "01111000" => --CLRZ
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '1';
                            ld_Z <= '0';
                            ALU_op <= "000";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01111001" => --ANDI
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "000";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "01";
                    WHEN "01111011" => --AND
                            clr_IR <= '0';
    ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "000";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "01111010" => --Checks for zero flag
                            IF (statusZ = '1') THEN
                                clr_IR <= '0';
                                ld_IR <= '0';
                                ld_PC <= '0';
                                inc_PC <= '1';
                                clr_A <= '0';
                                ld_A <= '0';
                                clr_B <= '0';
                                ld_B <= '0';
                                clr_C <= '0';
                                ld_C <= '0';
                                clr_Z <= '0';
                                ld_Z <= '0';
                                ALU_op <= "000";
                                A_Mux <= '0';
                                REG_Mux <= '0';
                                DATA_Mux <= "00";
                                IM_MUX1 <= '0';
                                IM_MUX2 <= "00";
                            END IF;
                        WHEN "01111100" => --Checks for carry flag
                            IF (statusC = '1') THEN
                                clr_IR <= '0';
ld_IR <= '0';
                                ld_PC <= '0';
                                inc_PC <= '1';
                                clr_A <= '0';
                                ld_A <= '0';
                                clr_B <= '0';
                                ld_B <= '0';
                                clr_C <= '0';
                                ld_C <= '0';
                                clr_Z <= '0';
                                ld_Z <= '0';
                                ALU_op <= "000";

                                A_Mux <= '0';
                                REG_Mux <= '0';
                                DATA_Mux <= "00";
                                IM_MUX1 <= '0';
                                IM_MUX2 <= "00";
                            END IF;
                        WHEN "01111101" => --ORI
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
    ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "001";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "01";
                        WHEN "01111110" => --DECA
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
    ld_Z <= '1';
                            ALU_op <= "110";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "10";
                        WHEN "01111111" => --ROR
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '1';
                            clr_Z <= '0';
                            ld_Z <= '1';
                            ALU_op <= "111";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
WHEN OTHERS =>
                            NULL;
                END CASE;

                    CASE INST(31 DOWNTO 28) IS
                        WHEN "0100" => --LUI
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '1';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "001";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "10";
                            IM_MUX1 <= '1';
                            IM_MUX2 <= "00";
                        WHEN "0101" => --JMP
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '1';
                            clr_A <= '0';
                            ld_A <= '0';
clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";

                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "00";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN "0110" => --BEQ
                            IF (statusZ = '1') THEN
                                clr_IR <= '0';
                                ld_IR <= '0';
                                ld_PC <= '1';
                                clr_A <= '0';
                                ld_A <= '0';
                                clr_B <= '0';
                                ld_B <= '0';
                                clr_C <= '0';
                                ld_C <= '0';
                                clr_Z <= '0';
                                ld_Z <= '0';
    ALU_op <= "000";

                                A_Mux <= '0';
                                REG_Mux <= '0';
                                DATA_Mux <= "00";
                                IM_MUX1 <= '0';
                                IM_MUX2 <= "00";
                            ELSE
                                clr_IR <= '0';
                                ld_IR <= '0';
                                ld_PC <= '0';
                                clr_A <= '0';
                                ld_A <= '0';
                                clr_B <= '0';
                                ld_B <= '0';
                                clr_C <= '0';
                                ld_C <= '0';
                                clr_Z <= '0';
                                ld_Z <= '0';
                                ALU_op <= "000";
                                    A_Mux <= '0';
                                REG_Mux <= '0';
                                DATA_Mux <= "00";
                                IM_MUX1 <= '0';
                                IM_MUX2 <= "00";
                            END IF;
                        WHEN "1000" => --BNE
                            IF (statusZ = '0') THEN
                                clr_IR <= '0';
                                ld_IR <= '0';
                                ld_PC <= '1';
                                clr_A <= '0';
                                ld_A <= '0';
                                clr_B <= '0';
                                ld_B <= '0';
                                clr_C <= '0';
                                ld_C <= '0';
                                clr_Z <= '0';
                                ld_Z <= '0';
                                ALU_op <= "000";
                                A_Mux <= '0';
                                REG_Mux <= '0';
                                DATA_Mux <= "00";
                                IM_MUX1 <= '0';
                                IM_MUX2 <= "00";
                            ELSE
                                clr_IR <= '0';
                                ld_IR <= '0';
                                ld_PC <= '0';
                                clr_A <= '0';
                                ld_A <= '0';
                                clr_B <= '0';
                                ld_B <= '0';
                                clr_C <= '0';
                                ld_C <= '0';
                                clr_Z <= '0';
                                ld_Z <= '0';
                                ALU_op <= "000";

                                A_Mux <= '0';
                                REG_Mux <= '0';
                                DATA_Mux <= "00";
                                IM_MUX1 <= '0';
                                IM_MUX2 <= "00";
                            END IF;
                        WHEN "1001" => --LDA
                            clr_IR <= '0';
    ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '1';
                            clr_B <= '0';
                            ld_B <= '0';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";
                            A_Mux <= '0';
                            REG_Mux <= '0';
                            DATA_Mux <= "01";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                    WHEN "1010" => --LDB
                            clr_IR <= '0';
                            ld_IR <= '0';
                            ld_PC <= '0';
                            clr_A <= '0';
                            ld_A <= '0';
                            clr_B <= '0';
                            ld_B <= '1';
                            clr_C <= '0';
                            ld_C <= '0';
                            clr_Z <= '0';
                            ld_Z <= '0';
                            ALU_op <= "000";
                            A_Mux <= '0';
                            B_Mux <= '0';
                            REG_Mux <= '0';
    DATA_Mux <= "01";
                            IM_MUX1 <= '0';
                            IM_MUX2 <= "00";
                        WHEN OTHERS =>
                            NULL;
                END CASE;
                ld_IR <= '0';
            END IF;
        END IF;
END process;
-------- STATE MACHINE ---------
PROCESS (clk, enable)
    begin
        --code for the state machine. Don't think it is relevant.
END process;
-------- DATA MEMORY INSTRUCTIONS ---------
PROCESS (mclk, clk, INST)
--code for enable and write-enable signals for read and write operations. ----Don't think it is relevant.
END process;
END description;

EDIT 4:

I think my code is now working:

enter image description here

In the picture above, you can see that data got loaded into registers A and B and the program counter is also experiencing increments of 1 with every clock cycle as I wanted.

I looked over my port-maps in my stand-alone CPU file again and I noticed a glaring error. I had set up the write-enable port of the system memory module to receive signal information from the enable port of my control unit. The picture of my defective CPU simulation wave-forms also shows that the write-enable port is active high all the time. I tackled this problem by setting the write-enable port equal to zero. After I did that, I started seeing favorable results.

\$\endgroup\$
  • \$\begingroup\$ Post exact error messages. Perhaps the Path needs to include these binaries. win+R>cmd>path \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Apr 15 '18 at 2:20
  • \$\begingroup\$ @TonyStewartEEsince1975 I received 1000's of warnings after compiling the code. I put them all in an editor document and put the link in my question. \$\endgroup\$ – a_sid Apr 15 '18 at 3:08
  • \$\begingroup\$ @TonyStewartEEsince1975 I am also not sure which path you are referring to. I also don't know what the extension of binaries is in quartus (Is it .qpf?). \$\endgroup\$ – a_sid Apr 15 '18 at 3:18
  • \$\begingroup\$ The errors you've included are in reference to the file "ControlUnit.vhd", which you haven't shown us in your question. \$\endgroup\$ – duskwuff Apr 15 '18 at 3:54
  • \$\begingroup\$ @duskwuff This link contains my code for the control path. I got those warnings when I ran my code for the top level entity file which is different. \$\endgroup\$ – a_sid Apr 15 '18 at 4:05
1
\$\begingroup\$

I had connected the Enable port of the control unit to the write-enable port of the memory module. This was causing that memory module's write-enable port to stay active high all the time after the first instruction got loaded into the IR. The write operation was probably active high all the time for the system memory after a brief initial time period. In essence, the write-enable port of the system memory module was getting the same information as the Enable port of the control unit.

In order to get around this problem, I set the write-enable port of the memory module equal to zero. As soon as I did that, the instructions after the first one started getting recorded and processed.

\$\endgroup\$

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