# How do processors control their clock speed?

I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power.

For something like a desktop processor where the clock speed can be changed to any desired frequency (within reason) - how does it physically do this?

• As alex's answer indicates, modern desktop CPU frequency is not continuously variable. It typically goes in steps of 100 or 133 MHz. (Related: how does a modern x86 CPU decide when to change frequencies, for "turbo" above the max rated speed, or if the OS hands off full control of power management to the CPU (Intel Skylake): SKL has an on-die microcontroller with as many transistors as a 486 did, just to make frequency decisions: Why does this delay-loop start to run faster after several iterations with no sleep? – Peter Cordes Apr 15 '18 at 19:47

This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL:

simulate this circuit – Schematic created using CircuitLab

The oscillator on the motherboard does not run at the CPU clock frequency, instead it runs at a frequency on the order of 100 MHz. This oscillator serves only as a known, stable reference frequency. Inside the CPU, the actual clock frequency will be generated by a voltage-controlled oscillator, or VCO. The VCO can be tuned to generate frequencies over a relatively wide range, but by itself it is not particularly stable or accurate - for a given control voltage, the frequency will vary from part to part and with supply voltage and temperature. A phase-locked loop then serves to lock the VCO output frequency into a specific relationship with the reference frequency.

The outputs of both the reference oscillator and the VCO are divided by programmable dividers (with a factor of D for the reference and M for the VCO output) and then compared with a phase and frequency detector (PFD). The output of the PFD is filtered and used to drive the VCO. This forms a control loop known as a phase locked loop, because it serves to drive the phase of the divided VCO to equal the phase of the divided reference. At the input of the PFD, the frequency will be $f_{PFD} = f_{ref}/D = f_{out}/M$. The result is an output frequency with a specific mathematical relationship to the reference frequency, $f_{out} = f_{ref} * M/D$. As can be seen in this equation, the frequency divider at the output of the VCO has the effect of multiplying the reference frequency by its division factor. This is how a PLL can effectively generate much higher frequencies than the reference frequency.

For example, assume the reference frequency is 100 MHz, the reference is divided by 1 (D) and the VCO is divided by 30 (M). This would result in an output frequency of 100 MHz * 30/1 = 3 GHz. This relationship can be changed by simply changing the divider settings, which can be done in software via control registers. Note that changing the frequency on the fly may not as simple as just changing the divider values, the frequency must be changed in such a way as to ensure that the CPU does not see any 'glitches' or clock pulses that are too short. It may be necessary to use 2 PLLs and switch between them, or to temporarily stop the clock or switch to another clock source until the PLL stabilizes at the new frequency.

PLLs are used all over the place to generate precise, easily tunable frequencies from fixed, stable references. Your Wi-Fi card and Wi-Fi router use them to select the appropriate channel by generating what's called the local oscillator frequency, a signal used internal to the radio to upconvert and downconvert the modulated data. Your FM radio most likely uses one to enable software control over the receive frequency, enabling easy recall of different stations. PLLs are also used to generate the high frequency clock signals used to drive the serializers and deserializers for Ethernet, PCI express, serial ATA, Firewire, USB, DVI, HDMI, DisplayPort, and many other modern serial protocols.

Your STM micro almost certainly has the second oscillator for the real-time clock. This lets the clock keep running (consuming minimal power) whilst the rest of the chip and the rest of the circuit is powered down. The device can then keep its clock and calendar running, and typically it can also restart the main processor on a timer too - all useful stuff for embedded devices.

• The real-time clock is usually much slower than the main clock (32kHz is typical), and because of this, the realtime clock oscillator and attached circuity can have very low current consumption. – mkeith Apr 16 '18 at 1:49
• @mkeith Low clock speed is important, sure, but predominantly it's because almost all of the processor is turned off. – Graham Apr 16 '18 at 21:05
• Graham, the original question is about why there are two oscillators. In principal, you could have partial shutdown with only one oscillator and you would save a lot of power that way. The reason there is a second lower speed oscillator is because dynamic power consumption is linearly correlated with clock frequency. So the dynamic power consumption of a 32kHz circuit will be around 300x less than the dynamic power consumption of a 10 MHz circuit. The reduced clock speed is an important part of the answer, in my opinion. – mkeith Apr 16 '18 at 22:45
• @mkeith It's not "in principal" - that's exactly how it works on every chip with a RTC. Of course the RTC part uses a lower speed oscillator to save speed. But the RTC part never uses the faster oscillator clock - it's an entirely separate circuit on the same piece of silicon; and likewise the rest of the chip never uses the slower oscillator clock. The RTC itself uses less power by running at a slower clock rate, sure, but the entire rest of the chip is 100% powered off and is taking zero current (well, nanoamps of leakage current, but that's all). – Graham Apr 17 '18 at 10:04
• @mkeith Sure, and I agree (although the frequency of RTC crystals historically comes from quartz electro-mechanical movements in clocks and watches, not from power-saving in electronics). I just wanted to clarify for the OP that the slower clock isn't for a "low-power" mode on the main processor - it's for an entirely separate peripheral. – Graham Apr 18 '18 at 16:46

very carefully !

CPU's have binary programmble prescalars and a PLL with VCO to drive the counter so that it multiplies the front-side-bus, FSB clock ( say 100MHz) .
This dynamic power saving mode is automatically selected when CPU useage is low with the right CPU drivers, CPU, OS and BIOS.

My i7 (8cpu) goes from 3101 MHz to 800 MHz and instantly steps 1100, 1300,1500... etc

If the Bios chooses x31 as in my case, then the CPU runs at 100MHz x 3100MHz and with a binary counter in the CPU choose from x8 to x15 to reduce CPU power at the same time as it regulates the CPU chip voltage in the 0.9V region all to conserve power.

I can display with my cursor in upper right corner on Win8.1 along with CPU % and memory %