I am currently working with an Arria 10 device (specifically a ReflexCES A10 SoM Indus module). The GPIO pins of the device are split into IO banks with specific VCCIO voltages controlling the banks.

We are quite tight for pins on the design we are working on, and on the SoM module pin headers there are a pair of differential IO pins that I would like to make use of for a pair of ~200MHz LVDS inputs. However, as they are on a bank which is shared with a DDR4 interface, the VCCIO is set to 1.2V. The Arria 10 doesn't support LVDS on a 1.2V IO Bank.

Having looked through the datasheets, the A10 devices support the following IO standards on a 1.2V bank: HSTL, SSTL-12, and POD12. Additionally as the pins are on a bank shared with a DDR4 controller, they can be configured for 48Ω or 120Ω calibrated termination resistor.

I've been unable to find a device which is designed for interfacing with any of the available standards by name using a DC coupled method - the LVDS lines are not scrambled so require DC coupling.

Upon further reading, it seems that POD12 (1.2V Pseudo Open Drain), the standard used by DDR4 controllers, actually seems to be relatively similar to CML in its termination scheme. Looking up some clock buffers, I find the Micrel/Microchip SY54016AR which is designed for re-driving 1.2V or 1.8V CML lines. Specifically it can take a DC coupled LVDS input, and convert it to a 1.2V CML line. The output can also be DC coupled using the following termination scheme:

CML to CML using SY54016AR

Based on the Arria 10 Handbook, when operating as a POD-12 receiver, it is designed to use one of the following two termination schemes. The lower one uses on-chip calibrated terminations which can be configured for 48Ω±15%.

Arria 10 Termination Schemes for POD-12

With a VCCIO of 1.2V, the two diagrams look to me to be compatible.

Furthermore, the re-driver has an eye voltage of 360mVpp up to 500MHz with common mode of ~0.6V. The Arria 10 requires >300mVpp swing, with a common mode of >0.2V.

So, my question is, will this work?

In order to test it we will have to spin a full PCB with assembly of some high density FMC connectors, so before going down that route, I'd like to get some confirmation that I'm not barking up the wrong tree.

Alternatively if you have any alternate/recommended approaches, those would be also welcome.


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