Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs.

For example, could not we just put the green construction in the place of red one? enter image description here

Here is my design after switching all MOSFETs according to description I have provided.

enter image description here

  • \$\begingroup\$ I know exactly where you got this diagram from. Microelectronic Circuits by Sedra and Smith. I have this textbook, too! :) I don't really use it for work though... Anyways, let's think about this. You (hopefully) know that the XOR function is \$Y=A\overline{B}+\overline{A}B\$... So what do you think the function will be if you didn't invert \$A\$ and \$B?\$ Hint: XOR almost like a combination of AND and OR functions. By the way, you do need 12 transistors total for the XOR gate, the textbook says you will need 8 with additional 4 to invert \$A\$ and \$B\$. \$\endgroup\$ – KingDuken Apr 17 '18 at 1:31
  • \$\begingroup\$ (When in doubt, run a simulation) \$\endgroup\$ – KingDuken Apr 17 '18 at 1:34
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    \$\begingroup\$ But I have also changed the MOSFETs. Normally A' goes into PMOS and this means whenever A is low, the switch will be off and whenever A is high, the switch will be on. So why not cancel the inversion and put an NMOS in front of A which will turn switch on whenever A is high and vice versa? \$\endgroup\$ – J. Doe Apr 17 '18 at 1:41
  • \$\begingroup\$ My apologies... I didn't see that you also changed some NMOS and PMOS devices... Oh boy... You're putting some PMOS devices in the pull-down network and some NMOS devices in the pull-up network. This will be messy to figure out what's going on. \$\endgroup\$ – KingDuken Apr 17 '18 at 1:43
  • \$\begingroup\$ I think what you are missing is that all pmos are connected to vdd, and all nmos to vss. That is the design driver for this arrangement \$\endgroup\$ – Henry Crun Apr 17 '18 at 2:01

NMOS can't really pull up that well, PMOS can't pull down.

An NMOS is controlled by \$V_{GS}\$, the voltage between the MOSFETs gate and source. In the original schematic, whenever the output should be low, all of the NMOS sources are pulled to ground (the transistors with floating sources will have had the sources pulled to ground by other NMOSs if the output will be low). Therefore, there will not be any problems getting \$V_{GS} > V_{th,N}\$.

In the second diagram, the top left NMOS has a floating source. If the source is at \$V_{DD}\$, the input \$A\$ would need to be at \$V_{DD} + V_{th,N}\$ to turn that transistor on. This is problematic.

  • \$\begingroup\$ Your entire answer assumes that the bulk/body is connected to source. \$\endgroup\$ – Harry Svensson Apr 17 '18 at 5:37
  • \$\begingroup\$ I've ignored all body effects. Does the common bulk used in IC invalidate what I've written? \$\endgroup\$ – andars Apr 17 '18 at 5:42
  • \$\begingroup\$ If I remember it correctly, the \$V_{GS}\$ changes to \$V_{GB}\$, with B connected to ground for NMOS and B connected to VDD for PMOS. This means that a NMOS can actually pull up and a PMOS can pull down. - But this is if I'm remembering it correctly. I can be wrong. \$\endgroup\$ – Harry Svensson Apr 17 '18 at 5:58
  • \$\begingroup\$ \$V_{GS}\$ does not change to \$V_{GB}\$. You seem to be describing something vaguely reminiscent of depletion-mode devices, which are not relevant to this question. NMOS transistors can pull up, they're just not particularly good at it. A NMOS device can only pull its source to \$V_{DD} - V_{th,N}\$, which is a show stopper for modern values of \$V_{th}\$ and \$V_{DD}\$. \$\endgroup\$ – andars Apr 17 '18 at 6:15

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