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i am trying to send(i2c mode) slave address to IN1307 it is sending 0XD0(add+write mode) after i am getting small spike at ack bit.

How to solve this spike at ACK bit?

Here pull up resisters i am using are 10Kohm.

  • \$\begingroup\$ does the spike cause communication to fail? \$\endgroup\$
    – R.Joshi
    Apr 19, 2018 at 9:09
  • \$\begingroup\$ as long as it happens AFTER the falling edge (passes Vlo) it does not matter \$\endgroup\$
    – Henry Crun
    Apr 19, 2018 at 22:04

1 Answer 1


Spikes on SDA here are not inherently problems. I2C is concerned with the state of SDA before/on the falling clock edge, which is where that data is latched.

SDA should not change state when SCL is high as this denotes Start or stoP

All a high like this (after/at the SCL falling edge, while SCL is low) tells you is that one device on the bus (master) released SDA to go high, before another device (slave) pulled it low. As long as the state is stable until the falling clock edge, it doesn't matter what happens when SCL is low. (In fact it is a time when multiple devices can assert low)

What you should be concerned by it the SCL rise time.

The SCL is slower than is desirable (for this clock rate) - remember the rising threshold is 70% of VDD - you are reaching that quite late.

Equally undesireable is that the SCL rise is much slower than the SDA rise. You should have similar time constants (R+C), so you don't cause clock skew between scl and sda.

It can be quite confusing to work out what is going on looking with a scope, as both master and slave can pull both SDA and SCL down. Here is a simple trick to make it easy to see which/both is driving a line. It talks about clock stretch, but it is equally useful just to be able to see what is going on, and understand it.

  • \$\begingroup\$ hi sir..! thanks for replay. Here i am checking i2c write mode wave forms in scientific SMO 1002 digital oscilloscope . is this possible to see the waveform in this scope? and i can see the only start bit +slave add(0XD0)+R/W bit+ stop bit in my scope. Here Address and data also i am sending to slave but in waveform i cont see the address and data . is there any problem in i2c initialization? please help me. \$\endgroup\$ Apr 17, 2018 at 9:26
  • \$\begingroup\$ It can be very difficult to use a scope and decode the waveforms. It helps a lot if you have a start pulse detector, then at least you are able to sync at the start of a message, and time from that. There is a schematic at the end of i2cchip.com/pdfs/BusMon.pdf. You can see the start detector is just a FF, so easy to lash up. \$\endgroup\$
    – Henry Crun
    Apr 17, 2018 at 10:00
  • \$\begingroup\$ No, IIC is concerned with the state of SDA at more than the falling edge of SCL. For normal data bits, SDA must be solid the whole time SCL is high. Data is generally clocked in on the rising edge of SCL, or read a little after the rising edge. The falling edge is only the time after which SDA can be changed again. Changes in SDA while SCL is high signal either start or end of message. \$\endgroup\$ Apr 19, 2018 at 6:08
  • \$\begingroup\$ @OlinLathrop Yes, that was very sloppily worded. corrected. No SDA is clocked in on falling SCL. see fig 46-19, time SP106 (0ns) ww1.microchip.com/downloads/en/DeviceDoc/40001869B.pdf#page=765 \$\endgroup\$
    – Henry Crun
    Apr 19, 2018 at 6:22
  • \$\begingroup\$ I thought data was sampled on rising edge but i guess it may depend on the specific processor? ww1.microchip.com/downloads/en/DeviceDoc/70000195f.pdf section 7.1 "All data bits are sampled on the rising edge of the clock." \$\endgroup\$
    – R.Joshi
    Apr 19, 2018 at 8:45

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