I am wondering how it is possible to build a sequential verilog circuit with a reset trigger. The problem I am having is that I need an always block specifically for when the reset is triggered. I have created this example of a counter to demonstrate what I mean:
`timescale 1ns / 1ps module Counter(input CLK, reset, output reg[2:0] val); always@(posedge CLK) val = val+1; always@(negedge reset) val = 0; endmodule
The bug I get when synthesizing this is
"ERROR:Xst:528 - Multi-source in Unit <Counter> on signal <Mcount_val_cy<0>>; this signal is connected to multiple drivers. Drivers are: Output signal of FD instance <val_0> Signal <val<0>> in Unit <Counter> is assigned to GND"
This is because val is updated in 2 always statements.
How can I work around this and have a sequential circuit with a reset trigger?