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I am using LM5060 from TI for switching big modular N channel MOSFET in SOT-227 package (IXFN420N10T) for relative high 100-200A loads.

On small loads like 10-20A it was working fine then we tried a bigger resistive load of around 50A and it was working completely fine when first connected when the gate was switched it was opened up and current flew and worked just fine. But then the gate of MOSFET didn't work anymore always opened.

Our schematic is based on the reference from datasheet with added 0.01uF capacitor on the gate.

Maybe someone does know why mosfet get's blown? It supposes to handle 420A and at 50A it blows (not literally but the gate doesn't work anymore)

EDIT: Here is schematic as asked

EDIT2: At first I saw in documentation that Vgate is like 12V so it was within the range, and now I see in further documentation it writes this but I don't really understand if I am understood correctly:

A charge pump provides bias voltage above the input and output voltage to enhance the N-channel MOSFET gate. When the system voltage is initially applied and both EN and UVLO are above their respective thresholds, the GATE pin is charged by the 24-µA (typical) current source. During normal operating conditions, the GATE pin voltage is clamped to approximately 16.8 V above the OUT pin (i.e. VGS) by an internal zener

So if I understood it charges voltage VIN - 16.8V ?

enter image description here

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  • \$\begingroup\$ Are you sure the gate voltage is within spec? \$\endgroup\$ – C_Elegans Apr 19 '18 at 20:48
  • \$\begingroup\$ Is this all you can tell us? \$\endgroup\$ – Sunnyskyguy EE75 Apr 19 '18 at 20:50
  • \$\begingroup\$ Schematic or it didn't happen. Your schematic, not a copy of a datasheet or app-npte. \$\endgroup\$ – brhans Apr 19 '18 at 20:50
  • \$\begingroup\$ Well, it's simple. You did something wrong. Of course, if you're not going to tell us exactly what you did, there's no way we can help. \$\endgroup\$ – WhatRoughBeast Apr 19 '18 at 20:51
  • \$\begingroup\$ How did you protect gate from excessive LdI/dt \$\endgroup\$ – Sunnyskyguy EE75 Apr 19 '18 at 20:51
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This type of circuit generates a ramp for the gate voltage which causes the output voltage to ramp. This limits inrush current due to capacitive loads. But there is a down side, while the voltage is ramping the MOSFET is operating in linear mode and subjected to stress of V*I. In your case the MOSFET you have chosen has Ciss of 47 nF which dwarfs the 0.01 uF you have added so the rise time will be about 100 ms. So half through the ramp, the MOSFET will be dissipating 441W (21V * 21A). There is a curve in the datasheet called SOA (safe operating area). At Vds of 20V the MOSFET can withstand 30A for 100 ms. So it possible you have exceeded SOA. It might worth putting a scope on the gate and source to see what the rise time actually is. You could try it with a load that is somewhat lower to see if it survives.

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