# Are there any drawbacks to this oscillator frequency multiplier circuit?

I'm trying to make an upconverter from 65 MHz to UHF band using a mixer; I therefore need an oscillator frequency around 375 MHz to mix with the 65 MHz base signal. I'm also trying to vary the oscillator frequency such that I can vary the upconversion from a final frequency of 420 MHz to around 450 MHz.

I found an I2C controlled oscillator that varies from 2.3 - 170 MHz that I'm hoping to use.

My intention is to NAND the oscillator with itself, producing a square wave of the same frequency, and then filter out the third harmonic to produce 3x the base frequency. Little has been chosen in the way of specific NAND gate IC or filter passives, but I wanted to see if anyone foresaw drawbacks or difficulties with this setup. Basic notion is below.

simulate this circuit – Schematic created using CircuitLab

Thanks!

• Traditionally, to get an increased frequency from a base one, you would use a PLL circuit. This is definitely an ingenious approach, I kind of liked it and you should at least prototype it. Watch for the NAND slew rate, output impedance and output amplitude. If the prototype doesn't work out as planned, go for the PLL. Apr 20, 2018 at 23:23
• @VicenteCunha it's a common enough method in a harmonic oscillator. Apr 21, 2018 at 17:20

Complex gates are not as fast, just use an invertor. 74AC04 will run at 125MHz, and has the lowest Z of cmos.

You can connect the unused outputs to GND and VDD to help lower the supply impedance

74Ac11004 had a nice centre power lead arrangement that made it great for this, they can deliver 200mW at 100MHz

I have used 74HC04 to triple 50 to 150MHz (before 74AC existed). To get decent power it was turned into more of an injection locked oscillator by putting a tuned circuit around it. This took it from a few mW, picking off harmonics, to ~50mW. I think it was like this - it was a very long time ago

simulate this circuit – Schematic created using CircuitLab

Of course you might find the traditional transistor multiplier uses far less power...

Yay, I'm all for unconventional approaches for electronics. You learn much more about the fundamentals getting something like this to work.

Don't think of it as 'NANDing the signal with itself', you're just simply putting it through an inverter, which is another name for a limiting amplifier. So you have low slew rate signal in, high slew signal out. That's what you need, high edge slew rates to give you significant energy at harmonics.

The degree of success you get will depend on the speed and power output of the logic gate. There are lots of very fast 'tiny logic' ICs out there. Choose an inverting buffer with a decent output, and run it at the higher end of its supply voltage range.

Good luck.

I wanted to see if anyone foresaw drawbacks or difficulties with this setup

I would consider a simple RLC filter like this (reasons why are below): -

Calculator source

This circuit has 27 dB peaking at 375 MHz. This means that the "wanted" output will be over twenty times higher than the fundamental and you'll have the benefit of a 2nd order slope to get rid of harmonics. That 2nd order slope will deliver -6 dB at the fifth harmonic and progressively much more attenuation at higher order harmonics.

I would consider starting this way because it's going to yield a better roll off of harmonics and, there are simple means of getting rid of the fundamental such as a notch filter or maybe even a series capacitor feeding the resistor will be enough.

Using two cascaded band pass filters will be a bit of a nightmare to tune and you'll get double humps in the AC response (due to filter interaction) that can only realistically be solved using a sim tool.

• It's also good to remember that the higher the Q, the longer the response and settling times. Apr 21, 2018 at 19:16