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enter image description here

Considering the last question in the image above:

What benefits does the LUT offer over discrete logic implementations ?

I was thinking that an LUT operation is a fixed time event something like O(1). I know that you can't use that metric to describe things on an FPGA but I was wondering if there was a similar metric ?

In addition to that would the benefits be that the LUT is faster than the discrete logic since a "computation" of the result is not necessary?

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  • \$\begingroup\$ It sounds from the caption below the diagram that the question is aimed at the timing hazards associated with such a discrete logic implementation. LUTs based implementations have different hazards. Reword the question as 'compare the timing hazards of the discrete logic and LUT implementation of the above function, do either have any advantages in an FPGA implementation?' \$\endgroup\$
    – Neil_UK
    Apr 21, 2018 at 6:20
  • \$\begingroup\$ I would say the main advantage is ease of reconfigurability. If you wanted implement arbitrarily reconfigurable discrete logic you would need a bunch of gates with a complex reconfigurable routing network. A LUT just condenses that down to a small RAM. \$\endgroup\$
    – alex.forencich
    Apr 21, 2018 at 6:22
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    \$\begingroup\$ A LUT is much slower then discrete logic. It is in fact an SRAM lookup table, which is many, many gates. Compare that to the 5 gates above. \$\endgroup\$
    – Oldfart
    Apr 21, 2018 at 6:45
  • \$\begingroup\$ A second LUT technique is using multiplexer trees instead of SRAM. \$\endgroup\$
    – Paebbels
    Apr 21, 2018 at 10:25
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    \$\begingroup\$ @oldfart: Not true! A LUT is just a multiplexer, which has only three stages of gate delay, regardless of the complexity of the function. Note that the FFs used to store the table data do not figure into the timing of reading it out. Their outputs are static, except during power-up initialization. \$\endgroup\$
    – Dave Tweed
    Apr 21, 2018 at 11:48

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