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This is a follow-up question on this, where I had asked about how one can implement multiplications without using any DSPs of the FPGA.

Now, I would like to know whether one can implement Quartus IP cores such as floating-point multiplier using ALMs (LUTs) instead of DSPs. I tried applying the answer to my previous question (i.e. (* multstyle = "logic" *)), but it did not work.

Is there a method for implementing the multipliers, adders, and MACs in the IP library using logic blocks rather than DSPs?

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This is up to the design of the core. If there are configuration options for the core that determine how the internal operations are implemented, then yes, just configure the core however you like. If not, then no, there is no way to do that. IP cores are generally black boxes to the FPGA toolchain. They are usually synthesized separately and can do all sorts of stuff including direct instantiation of device primitives. When your design is synthesized, all the toolchain gets for the IP core is a netlist, and if that calls for a DSP slice, then that's what you get.

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