# How to implement Quartus IP cores using ALMs?

This is a follow-up question on this, where I had asked about how one can implement multiplications without using any DSPs of the FPGA.

Now, I would like to know whether one can implement Quartus IP cores such as floating-point multiplier using ALMs (LUTs) instead of DSPs. I tried applying the answer to my previous question (i.e. (* multstyle = "logic" *)), but it did not work.

Is there a method for implementing the multipliers, adders, and MACs in the IP library using logic blocks rather than DSPs?