# getting error from for loops in vhdl

Hi I am trying to use 2 nested for loops in vhdl but I get this error.

[Synth 8-561] range expression could not be resolved to a constant [318]

I do not understand why this code is not working since cursor_pos_x or cursor_pos_y are not constants.

this is the for loops I have

   for i in (cursor_pos_x) to (cursor_pos_x + length - 1) loop --318
for j in (cursor_pos_y) to (cursor_pos_y + length - 1) loop


cursor_pos_x and cursor_pos_y are signals and have integer type. and length is

signal length : integer range 0 to 250:= 250
signal cursor_pos_x : integer range 0 to 250 := 0;


How can I fix this?

• Please edit your question to add which software tool is giving you this error plus much more about your design. At first glance, I'm suspecting that you're treating loops like software programming for loops, not hardware description language for loops. But wider detail about the rest of the VHDL design should reveal if it is a misconception or a design fault. Apr 21, 2018 at 19:18

The problem here is that you are designing code for synthesis without really understanding what that means.

Synthesis generates hardware to implement your design : think about the implications of a loop whose range is not constant : it implies that, as you change the loop limits, hardware magically appears or disappears to implement that change.

Ain't gonna happen; at least not in today's FPGAs.

So, you have to transform your algorithm to one with static loop constraints.

For example, you can transform

for i in cursor_pos_x to cursor_pos_x + length - 1 loop
do something;
end loop;


into

subtype my_loop_range is natural range min_x to max_x;

for i in my_loop_range loop
if i >= cursor_pos_x  and i < cursor_pos_x + length then
do something;
end if;
end loop;


Now you always loop over the entire range, but only if two comparators comparing the loop index with your variable (or signal) bounds say "yes", will the do_something block be enabled.

While loops are worse : there is in general no definite loop limit, so synthesis tools may support them even more poorly.

Incidentally, you do realise that (in a clocked process) your loop will be completely unrolled, generating enough hardware to run the whole loop in a single clock cycle, right? If you have two nested loops with 250 iterations each, that'll be quite a lot of hardware...

• I truly thank you for the idea you have just given to me. I understand you but I still do not know how to reduce hardware. You said that will be quite a lot of hardware. How can I make my project more efficient? Apr 21, 2018 at 20:50
• HUGE topic. But here's a first pass at an answer. stackoverflow.com/questions/14666649/… Apr 21, 2018 at 21:04

I do not understand why this code is not working since cursor_pos_x or cursor_pos_y are not constants.

That is exactly the problem. If you look at the error message it says:
range expression could not be resolved to a constant

Your for loop uses variables. You have given them a default value but that does not make them constants. For synthesis the loop range must be static (i.e. implies a definite number of iterations).

• may I use while loop, variables and if statements? because range must be dynamic. it cannot be static. Apr 21, 2018 at 20:04
• I don't know what the rest of the code is but I am 99% sure that will not work. You might need a state machine or something like that which takes e.g. N clock cycles to work through the loop. The value of N can be dynamic. Apr 21, 2018 at 20:12

The range in a for loop should be constants to be able to synthesis it. Vivado synthesizer throws error because its unable to resolve the dynamic ranges in its expression formed by cursor_posx and length.

The loops are unrolled while synthesising to replicate hardware. So the bounds have to be definite and well known to the synthesizer. There is no definite bound here in your code.

• may I use while loop, variables and if statements? because range must be dynamic. it cannot be static. Apr 21, 2018 at 20:04
• As @Oldfart says, you have to implement state machine. N iterations --> N clock cycles Apr 21, 2018 at 20:42