If there is a power cut to the CPU, will be registers clear or keep their memory?
Normal flip-flops are volatile, in that they don't remember their state when power is lost. Usually CPU registers are made from such flip-flops, which is why you need to save stuff you want to remember accross a powerdown to special memory for that purpose. Since non-volatile is a important attribute, this will be clearly mentioned in any datasheet for a non-volatile memory. If it doesn't say it's non-volatile, then it's volatile (data lost on power down).
Nowadays, most non-volatile memories are EEPROM (Electrically Erasable Programmable Read-Only Memory). Flash is a type of EEPROM that you often hear about. It has tradeoffs that make it cheap for large memories, usually at the expense of write speed and total number of lifetime writes before it wears out.
Some flip flops and latches are specified to always come up in a known state when power is first applied, if the power voltage waveform meets certain requirements (typically it must start below some voltage and rise monotonically until it has reached some higher voltage). If the power supply voltage changes in a way which does not meet that criterion, the device may or may not be reset to a known state.
For many other flip flops and latches, however, the behavior when when the supply voltage falls below the stated requirements is completely unspecified. As such, if a latch was high when power was switched off, it may or may not be high when power is switched back on. Likewise if it was low when power was switched off. Some such devices are "biased" so that when they are switched on they will likely to power up in a particular condition. Some others, however, are not. It is sometimes possible for a CMOS latch to "remember" its state for many seconds or even minutes when the supply voltage is zero or close to it. What happens, typically, is that each latch contains a pair of logic gates which are wired so that when one is on the other will be forced off. On power-up, both gates will start to switch on until one succeeds, whereupon that gate will force the other one off. If the two gates are well-matched and neither has any residual charge, the power-on state may be largely random, but if either state has any residual charge left over from the last time the device was powered on, that residual charge may cause the latch to power up in the state it last held.
Incidentally, it's possible to design a latch with internal capacitors that will bias its power-on state to the opposite of its last state. I've never seen this done with chips, but I have seen it done with latches made from discrete transistors; such circuits can be useful for things like divide-down counters.