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I tried building a JK flip flop from logic gates. This is my schematic design:

enter image description here

However, my waveform for the case J=1, K=1 does not have the Q toggled. Instead, Qnot just copied completely CLK in that situation.

This is my waveform:

enter image description here

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  • \$\begingroup\$ In the schematic editor, you should end your wires at the edge of each block. You shouldn't see a blob on each symbol connection - that means you've drawn the wire too far. Shouldn't be causing the problem, but worth noting. \$\endgroup\$ – Tom Carpenter Apr 23 '18 at 14:27
  • \$\begingroup\$ @DonFusili they are connected. The output of inst2 shows actually what it should look like - the wire stops at the symbol rather than drawing over the top of it. \$\endgroup\$ – Tom Carpenter Apr 23 '18 at 14:28
  • \$\begingroup\$ The bigger issue is that you are trying to make flip flops out of gates in an FPGA toolset (quartus). Don't do this. You should not be trying to make flip flips out of logic in FPGAs, they have register primitives. \$\endgroup\$ – Tom Carpenter Apr 23 '18 at 14:29

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