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I have a basic question for advanced FPGA developers: Do I need to use special synchronisation code for FPGA inputs?

I mean, the input will be checked in a synchronous process. Outside of the FPGA, input signals can change at any time (freq is much lower than the clock of the FPGA). Does the FPGA have some special input implementation which considers this (I am using Microsemi Proasic3) ?

If a special treatment is necessary, how should I do it?

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One common technique to ward against potential metastability issues, which can result in cases like this, is to double register your inputs. Like this:

double register credit: Altera whitepaper

Metastability is a phenomenon that can cause system failure in digital devices, including FPGAs, when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This paper describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it can cause design failures. The calculated mean time between failures (MTBF) due to metastability indicates whether designers should take steps to reduce the chance of such failures. This paper explains how MTBF is calculated from various design and device parameters, and how both FPGA vendors and designers can increase the MTBF. System reliability can be improved by reducing the chance of metastability failures with design techniques and optimizations.

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You need to sanitize your inputs to avoid metastabilty (voltage in between high and low). This can be done in a few ways, one way is a dual rank synchronizer (However the input would be connected to the synchronization chain block, the result is the same): enter image description here
Source: Wikipedia

The proasic3 also has the ability to enable schmitt trigger inputs on its gpios which will force the signal to go high or low, but not sync it with the clock, so you still need some kind of clock synchronization.

enter image description here Source: Proasic3 I/O guide

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  • \$\begingroup\$ You only "need" to do this if your timing slack is low. Depending on your platform, metastability events can be considered a non-issue beyond 5-10 ns (you'll have to ask an Apps engineer to know for sure), so at a slow clock speed there's no need to double/triple sync. It's still important to have at least one synchronizing flip-flop though, just to keep the signal coherent within your system. Most FPGAs have a FF right at each IO that can be used for this purpose. \$\endgroup\$
    – jalalipop
    Apr 25, 2018 at 16:44

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