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The question is as follows:

Identify and explain two potential advantages and disadvantages of loop "unrolling"

While searching the internet I came across these two resources:

  1. Resource One
  2. Resource Two

But all I could really discern from them is that loop unrolling allows parallelism to occur in the system and not really why this is a good or bad thing. Although I know that the whole point of an FPGA is allow things to run in parallel, a feature (loop unrolling) that makes this possible doesn't seem like an advantage.

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3 Answers 3

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From the abstract of your second link:

Loop unrolling is the main compiler technique that allows reconfigurable architectures [to] achieve large degrees of parallelism. However, loop unrolling increases the area and can potentially have a negative impact on clock cycle time. In most embedded applications, the critical parameter is the throughput. Loop unrolling can therefore have contradictory effects on the throughput. As a consequence there exists, in general, a degree of unrolling that maximizes the throughput per unit area.

To me, this directly answers your question. The idea is basically this: if you have a process which must iterate over many cycles, you can employ loop unrolling to parallelize the algorithm to reduce the number of required clock cycles.

But this comes at a cost of a larger fabric footprint (more FPGA area), which in turn complicates clock routing leading to more difficult timing closure.

If timing closure can’t be obtained, the system is forced to use a slower clock frequency, which conflicts with the goal of unrolling.

Therefore, you have to find a balance between the two to maximize the gain in performance.

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  • \$\begingroup\$ I see, for some reason I was thinking that loop unrolling was just for the compiler to translate the code and the translation wasn't physically implemented on the FPGA. I can see now how that doesn't make sense. \$\endgroup\$
    – SRR
    Apr 25, 2018 at 6:02
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It's the only way a synthesis tool can implement an entire loop either in a single clock cycle (in a clocked process) or combinationally.

So advantages and disadvantages over other (non-existent) methods of translating a loop are a moot point.

It can, as already stated, generate rather large hardware. If that's a problem you need to find another coding approach, for example replcing the loop with a state machine to execute one iteration per clock cycle, for smaller (but slower) hardware.

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  • \$\begingroup\$ Won't the state machine still have to run whatever logic you needed in the first place ? Or do you mean actually breaking up the loop 'increments' to a different state machine for each increment value ? \$\endgroup\$
    – SRR
    Apr 25, 2018 at 8:36
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    \$\begingroup\$ Yes of course.. \$\endgroup\$
    – user16324
    Apr 25, 2018 at 8:38
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'Loop Unrolling' is a systematic method of achieving parallelism that can be automated.

In the bad old days, we wrote machine code, then assembler, then simple compiled languages, then rich languages with useful libraries. This allowed us to write at a progressivley higher level, and let an automatic process take care of the translation to low level.

In the bad old days, we'd write VHDL, and then manually put several blocks in parallel to get the throughput, and manually schedule their operation, pipeline data, to get them to work. Expressing our intention as a high level loop and then letting an automatic process generate the low level timing and dependency ordering is simply applying the same automation principle to hardware design.

Advantages - speed, accuracy, humans like to think at high level.

Disadvantages - humans have this nagging feeling that because 'this bit here' looks inefficient, they could do it better. That's often correct, with early generation tools. It takes time for the interface to the tools to become easy to use, for the tools to become trusted, and for their performance to improve to the point that no corners remain where human tweaking might still be warranted.

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