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We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this?
Of course, the frequency itself can't be changed for given logic gates, but can I make a clock from this by giving high inputs at CLK,J and K? (I don't care about the exact frequency, it should just be like in MHz)

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  • \$\begingroup\$ Possibly, but there are more reliable ways to make oscillators, why go for this way? \$\endgroup\$ – immibis Apr 26 '18 at 3:07
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You can not use a JK or any other Flip-Flop unless you already have a clock.

Thus you can make a new clock signal with a lower frequency but not higher. The nearest is a divide-by-two. Thus new_freq = old_freq/2. With more FF's you can make a divide by 4,8,16 etc.

With some extra gates you can make a divide by 3, 5, 7.
You can not make a divide by a fraction unless you start using more special circuits like a PLL.

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A J-K or any D type flip-flop will not generate a clock of its own. Tying J and K together create a D type flip flop with the outputs fed back to input so it toggle on the rising edge of a clock pulse, just like the D type will do if /Q is tied back to the D input. You can chain them together with /Q output tied to the clock input of the next stage, which gives you a simple ripple counter.

You can use a CMOS 555 timer to get a basic clock pulse to experiment with.

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