The Xilinx web page for the FIFO Generator IP states:
Key Features and Benefits
- FIFO depths up to 4,194,304 words
- FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
This is certainly a mistake, but I'm asking for confirmation in case I am missing something.
The IP's documentation states that the depth is up to 131,072 - which I believe is correct.
- Supports Native, AXI4-Stream, AXI4, AXI3 and AXI4-Lite interfaces
- FIFO depths up to 131,072 words
1 FIFO Generator v13.2, LogiCORE IP Product Guide, PG057, p. 9