The Xilinx web page for the FIFO Generator IP states:

Key Features and Benefits

  • FIFO depths up to 4,194,304 words
  • FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
  • ...

This is certainly a mistake, but I'm asking for confirmation in case I am missing something.

The IP's documentation states that the depth is up to 131,072 - which I believe is correct.

Common Features1

  • Supports Native, AXI4-Stream, AXI4, AXI3 and AXI4-Lite interfaces
  • FIFO depths up to 131,072 words
  • ...

1 FIFO Generator v13.2, LogiCORE IP Product Guide, PG057, p. 9

  • \$\begingroup\$ Sorry but I can't help it: this question reminds me of Space-balls with Ridiculous speed an Ludicrous speed! Both FIFO depths are theoretical numbers and are unlikely to be used practically. \$\endgroup\$
    – Oldfart
    Apr 27 '18 at 17:31
  • \$\begingroup\$ @oldfart First: hilarious. Second: in my case, they are not theoretical, and I wish it was the Ludicrous value. I'm testing a PXIe 1-PPS time-interval counter card, and need to generate two 1-second pulses, one with a large offset delay. It's just a quick, simple design and I don't care if the entire fabric is filled up with a giant FIFO. But for a decent range of delays and good resolution, with a 100 MHz clock, the larger the FIFO the better. \$\endgroup\$ Apr 27 '18 at 17:41
  • \$\begingroup\$ Sounds like you need two registers to store the start and end times of the pulse (if they are independent) rather than a FIFO to store the sampled signal. \$\endgroup\$ Apr 28 '18 at 10:59
  • \$\begingroup\$ @BrianDrummond I’m not measuring the pulses, that’s the job of the TIC counter, I’m just slewing them around to test various delay conditions. The signals are output from my board through coax and then into the TIC. It’s pretty simple, and already done. \$\endgroup\$ Apr 28 '18 at 13:38
  • \$\begingroup\$ Ah but if you measure them, you can regenerate them any later time you want, with minimal storage. (It's more complex if you have many pulses in flight at once, of course). \$\endgroup\$ Apr 28 '18 at 13:54

You can easily cascade FIFOs. So the maximum FIFO depth is more determined by the amount of memory on the FPGA then maximum size of the IP.

For very big FIFO depths you can add a DDR interface to the Xilinx** and use the DDR as FIFO. It requires an AXI DMA write and read channel each starting with a certain delay between them.

**Or buy e.g. a Zynq which has a built-in DDR interface.

Almost forgot: the FIFO depth as specified in the Xilinx IP are related to the data width. I think the maximum depth are for 8 bit wide data.

  • \$\begingroup\$ Sure, I understand this and it's good info. But my question was really just to confirm the webpage typo for a single FIFO instance. If I'm going to daisy chain FIFOs, I should at least ensure that I'm using the maximum capacity of each before the final stage. \$\endgroup\$ Apr 27 '18 at 17:53
  • 1
    \$\begingroup\$ Actually, I abandoned the IP anyway and just made the fifo from RAM. \$\endgroup\$ Apr 27 '18 at 17:55

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