This is a basic block diagram of source synchronous interface I found in altera document.
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the clock to meet setup and hold requirement. So I think it means the clock edge that is sent aligned with the data is latching edge or next clock edge. NOT the edge it used to launch the same data. Ha but the diagram given by altera (at the first), looks like it sends the same launching edge aligned with the data.
Then there is one more statement I found.
"Source synchronous interfaces often exhibits different behavior. Data may be latched by the same edge that launches it".
How is that possible. Is not this a hold violation ? I am Confused on which clock edge is sent edge aligned with data. Is it the same launching edge or next latching edge ?