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This is a basic block diagram of source synchronous interface I found in altera document.

Here

This is how edge aligned source synchronous output looks like.

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They say the reciever will shift the clock to meet setup and hold requirement. So I think it means the clock edge that is sent aligned with the data is latching edge or next clock edge. NOT the edge it used to launch the same data. Ha but the diagram given by altera (at the first), looks like it sends the same launching edge aligned with the data.

Then there is one more statement I found.

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"Source synchronous interfaces often exhibits different behavior. Data may be latched by the same edge that launches it".

How is that possible. Is not this a hold violation ? I am Confused on which clock edge is sent edge aligned with data. Is it the same launching edge or next latching edge ?

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  • \$\begingroup\$ Fig 1 and Fig 2 in the Altera document are basically incompatible and I think this gives you confusion. Fig 1 must produce a clock pulse for each data bit and this then makes Fig 2 look stupid. \$\endgroup\$ – Andy aka Apr 28 '18 at 18:11
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    \$\begingroup\$ Some devices have zero (or even negative) hold time requirements. \$\endgroup\$ – WhatRoughBeast Apr 29 '18 at 0:47
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    \$\begingroup\$ Yea if skew is negative compared the launching flop, hold time will be negative for the capturing flop. But still no hold violation is there because the data is ensured to be captured in the next clock edge. Here they say capturing edge can be same as launching edge. \$\endgroup\$ – Meenie Leis Apr 30 '18 at 7:35
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In system synchronous interfaces, that is indeed a hold violation cz normally we want everything to be captured ONLY on the next clock edge.

In edge aligned source synchronous interfaces, clock is regenerated and fed to the receiver along with the data with minimum line to line skew.

A sample from the same document:

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The launching clock and the capturing clocks are hence two clock domains. Whether setup/hold has got violated or not depends on what is our desirable operation in this circuit.

Here our desired operation is to capture the data in the same clock edge which is transmitted along with the data. Hence our setup check will be between the SAME edges and hold check will be between the launching edge and the clock edge BEFORE it. But by default timing analyser will check setup and hold between next and same edge respectively. So We tell our requirement to the timing analyser using multipath constraint:

enter image description here

Timing constraints can be complex for source synchronous. The documents seems to cover every aspect well.

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Some units such as DDR memory use both edges of the clock to access data faster by inverting clocks and multiplexing from two registers to maximize thruput.

Regardless of wherther it is Double Data Rate or single edge clock memory such as a simple synchronous bus latch, the sync characteristics are always given in the spec. and defined by active edge , latency, setup and hold time.

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