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Why is a control signal MemRead needed for the Data Memory element if whenever the output Read Data is not desired it will be multiplexed out via MemtoReg?

Wouldn't having MemRead always enabled just cause Read Data to always output whatever is currently stored at targeted address, making it readily available to be used if required, or ignored if not required via the multiplexer?

Does Data Memory, being sequential, only execute on a clock edge and cannot complete two tasks at once like this? Isn't it true that combinational elements such as the ALU always output f(input1, input2) regardless of clock edge?

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Wouldn't having MemRead always enabled just cause Read Data to always output whatever is currently stored at targeted address

Yes, it would output whatever is stored at the targeted address, but the targeted address might be from the last write operation.

or ignored if not required via the multiplexer

If the multiplexer is set to 0, the address will be output. If you want to hold the read value constant while write operations are happening, you would need to set MemRead low, and the mux selector, MemtoReg high.

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Yes, if it's static RAM, it could just send whatever is addressed to the multiplexer always.

However, if it's DRAM, then it needs periodic refresh cycles. If the refresh is generated internally in the "memory" black box, then giving it both a read and a write signal allows it to know when it can safely take time off to do a refresh step.

Another explanation would be that it has to do with timing. Perhaps the memory needs several cycles to work, and the data path can be used for something productive meanwhile (assuming that the memory latches the address internally)?

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    \$\begingroup\$ Additionally, some memory-mapped registers have side effects when you read them. \$\endgroup\$ – immibis Apr 28 '18 at 23:04

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