How closely do you pack your thermal vias? I know that more vias divides the amount of heat each via can move and that smaller vias allows more vias to be packed together. Knowing this, it seems like more vias are better for thermal dissipation.

There are diminishing returns for the amount of vias that are placed, but assuming that you can place as many as you want without accruing extra manufacturing costs, how many vias can you place before compromising the structural integrity of your board? (assuming using the standard fr4 board substrate at a standard 1.6mm thickness)

Should they be placed in a pattern? What do you do personally? Does everyone just choose a target amount of watts to dissipate through the board from the junction and make the minimum amount of holes?

  • \$\begingroup\$ Like most things, the answer is "it depends", the rule of thumb I've been told is "once you have 3 to 4 rows of vias on a side, adding more doesn't achieve much if the PCB is the heatsink". Having said that, with a physical heatsink bonded on one side of the board more vias will conduct more heat, but most manufacturers have limits on how close you can space holes reliably. Don't forget that excessive vias and solid copper planes can make soldering much more difficult (especially with thicker copper e.g. 2oz, 4oz etc.) \$\endgroup\$
    – Sam
    Apr 28, 2018 at 22:42

5 Answers 5


I use this document by Cree as reference. They provide some measurements, and from these measurements I make some ballpark assumptions.

It has multiple scenarios considering different via sizes, PCB thickness, amount of vias, etc.

Note that these are "Solder point through board" Thermal resistance measurements, so I believe they do not account for heat dissipated through a larger copper plane, just transfer through the board.

Also, the size of the device will probably influence a lot the amount of vias that are effective, since packages with thermal pads will help a lot lateral heat carry, making move vias more useful, so this is mostly valid for devices about the size of these LEDs.

This chart would indicate that for 1.6mm FR-4, 15 ~0.4mm vias seem to be the point after which larger vias and/or more of them give diminishing returns.

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This next chart seems to indicate that around 4mm trace width (that is, something like a ~4mm thickness ring around a heat spot, see figure 12 and 13), the PCB loses a lot of capacity to transfer heat laterally:

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In their recommended layouts for LEDs, they use 0.254mm vias spaced 0.635mm apart.

If you put 16 0.4mm vias in a 4x4mm square rectangle (larger distances would hinder lateral heat transfer drastically), this would give a maximum pitch of 1mm. The minimum pitch would be the minimum inter via distance + your desired margin.

There are other documents (such as this one by on semi) that cover PCB plane size for different layer counts. Arguably they provide diminishing returns around ~40mm for multilayer boards. (I believe its less for 2 or single layer boards due to lower lateral heat transfer capacity).

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How closely do you pack your thermal vias?

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The above I would consider borderline excessive. That is, if the pads with holes, were directly under the thermal pad.

  • Too many holes
  • Holes too close to each other (or too big)
  • Holes too far away

Holes should be 10 mil in diameter and spaced 25 mil apart. That leaves 15 mils of copper between vias . The diagonal holes have less copper than the diameter of the vias. It appears the vias may be too big.

The vias in contact with the thermal vias are the only really effective vias. Vias further than 3 mm from the thermal pad are ineffective. The copper not under the thermal pad is best used for convective and radiation heat transfer.

This is actually a horrible thermal design. The thermal vias should be on the thermal pad. The thermal area (the A in Fourier's Law) is the cross sectional area of the copper's thickness. PCB copper is too thin for sufficient conductive heat transfer. In this design, the heat transfer is first lateral then through the vias. The lateral heat transfer is unnecessary, inefficient, and ineffective.

Thermal Vias Points of Diminishing Returns Bottom Line

  1. 10-15 mil diameter holes (10 better than 15)
  2. hole centers spaced 25 mils apart
  3. Location of holes directly under the thermal pad, no further than 3 mm from the thermal pad.

it seems like more vias are better for thermal dissipation

The diminishing returns are significant so drilling holes to the point of causing wakened mechanical integrity is pointless.

So more holes is not better, more like useless.

There are two variables in the thermal dynamics conduction formula (Fourier's Law) where you can still improve.

  1. Area: thickness of the via copper
  2. dx Length/Distance: Length of via/thickness of PCB

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If you have not done so, reduce the thickness of the PCB. By going from 0.062" to 0.031" you reduce via thermal resistance by 50%. I used 0.020" boards.

The Cree Optimizing PCB Thermal Performance documents referenced in a previous answer (@Wesley Lee) is very good. A few years ago I spent a lot of time researching thermal vias and found a lot of studies on the topic. The Cree document is a great summary of what I found elsewhere.

Also from the Cree document.
I think the number of holes is very relevant here. It shows the diminishing returns.

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Much of the current research on thermal vias have been done for LED.

Even though they cannot spell platform, there is a good section on vias.

LUXEON Rebel Plaform Assembly and handling information

From the above document on number of holes and diminishing returns.

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OSRAM has a nice little theraml management primer on Conduction, Convection, and Radiation.
OSRAM App Note: Thermal Management of Light Sources Based on SMD LEDs

Example from OSRAM
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I do high power LED strips and the thermal vias did not help much. I concluded thermal vias were inadequate to conduct thermal flux.

What I had to do is mount the heatsink or a copper bar to the component side of the board as close to the heat source as possible. I never tried aluminum because I would leave bare copper where the bar connected to the PCB and was concerned about electrolysis. I now (got first PCB this week) use ENIG rather than bare copper so I can now try aluminum.

There is are alternating Cree XP and Lumiled Rebel footprints on this strip. The pads with the holes are the thermal pad. The screw holes for the heatsink are about 0.128" for the 4-40 machine screw.

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This is how well the thermal vias worked:

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Below is the heatsink mounted to the PCB. The heatsink here is a copper water pipe with cold water being pumped through it.

This approach was to have 100% thermal conduction where the thermal path was 100% copper.

I left the thermal vias in place to measure the temperature of the thermal pad.

The point is mounting the heatsink to the component side (if posible) is much better than thermal vias.

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In testing the copper bar and the water pipe were almost the same temperature. The measured test points are below. Ice water water was pumped through the copper pipe.

The thermal pad, left most point, 10°C higher than the pipe right most. The point between the screw and thermal pad was a few degrees higher than the copper pipe.

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It depends where the heat goes after the vias.

If the back side of the board is a real heatsink, then it's worth continuing to add more and more vias through the board to shift heat from the topside. As you add more and more vias, the board becomes more like metal and less like FR4. The board thickness and composition will still be the limiting factor.

If the vias are to distribute heat to the board ground planes, and from there sideways and to the air, then there's little point in cramming lots of vias in, as it's the subsequent heat path that's the limiting factor.


A square of 1 ounce/foot^2 copper foil ---- 35 microns thick, or 1.4 mils thick ----- has 70 degree Centrigrade/watt of thermal resistance.

For any size square of foil. 1 meter square, or 10mm square or 1mm square.

Vias are plated to be approximately the same internal-wall thickness as the foil at both ends of the via, from the micro-cross-sections I've seen.


simulate this circuit – Schematic created using CircuitLab

A via has an easily computed thermal resistance. A 0.06 long via ( thru 1/16" FR-4) with diameter 0.02" (circumference of Pi * 0.02 = 0.0628) is a SQUARE piece of plated-copper, and thus has thermal resistance of 70 degree Centigrade per watt.


Each via has a better thermal conductivity than the FR4 substrate, so more vias give obviously a lower thermal resistance and therefore provides a better heat transfer. More, each via has an inductance, so having many them in parallel makes a better electrical connection of bottom slug of a IC if it also serves as ground connector.

So, I would conclude, more vias is better, up to manufacturing limit/drill spacing, and smaller filled vias are better too. Regarding the pattern, placing more vias in areas of higher thermal stress would be better too, so maybe only certain areas of a design should have many of them.


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