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I find the 'Physical View' provided with most FPGA tools somewhat mesmerizing for a complex design. Tens of thousands of switchboxes, LUTs, latches and multiplexers all configured from the HDL. It would be great to combine a logic simulator with the post-P&R layout to animate the physical view with 1/0 signals rippling through the design as stimulus is presented. This would also provide a "visual check" that the trace tools are actually making valid measurements of the timing. A slow motion view could show the clock/data race through the design so you can see the longest path lose the setup race against the clock.

It would make an educational video for teaching timing. So, why isn't this done? Other than the tools are fiendishly complicated already and functional correctness is difficult enough without worrying about animation?

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  • \$\begingroup\$ In a complex design like you're talking about, animation would likely (at least historically) eat up processor time that most customers would rather be spent on running the actual simulation. \$\endgroup\$ – The Photon Jul 2 '13 at 19:29
  • \$\begingroup\$ I think you mean mesmerizing, not memorising. Other than that, the comments by Photon and Brian Carlton are spot on. \$\endgroup\$ – Joe Hass Jul 3 '13 at 0:42
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Because it wouldn't add value for their customers. It would only be "eye candy" at best. It is easier to debug at the RTL level than at the gate level. Also simulation is faster at the RTL than the gate/LUT level.

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