I just learned about memory segmentation that is used in microprocessors and I was told that old microprocessors like Intel 8086 had 20 lines of address bus which means that it could access 2^20 memory location.

If 20 lines bus is necessary to access a memory of 1 MB how can a microprocessors access let's say 1TB of memory? Because obviously it seems absurd to make so many lines to access that huge memory.

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    \$\begingroup\$ The standard size nowadays is 64 address lines, which allows you to access 2⁶⁴ memory locations, which comes out to 17 million terabytes. \$\endgroup\$
    – Hearth
    Apr 29, 2018 at 14:59
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    \$\begingroup\$ @Felthry, sounds like you mean 'standard' for microprocessors used in PCs/workstations, servers etc... \$\endgroup\$
    – TonyM
    Apr 29, 2018 at 15:04
  • \$\begingroup\$ @TonyM Fair point. But your microwave doesn't need a terabyte of memory! \$\endgroup\$
    – Hearth
    Apr 29, 2018 at 15:07
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    \$\begingroup\$ "Because obviously it seems absurd to make so many lines to access that huge memory." no, it's not, do the math before you claim that. \$\log_2 10^{12}= 12 \cdot\log_2 10 \approx 12 \cdot 3.3=36\$ really isn't all that absurd. \$\endgroup\$ Apr 29, 2018 at 16:09
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    \$\begingroup\$ Each address line you add to the system doubles the amount of physical memory that the system can (theoretically) use. So, 20 address lines gives you access to 1Mb. 21 address lines gets you 2Mb, 22 gets you 4Mb ... 30 address lines gets you 1Gb, and 40 lines are enough to address one Terabyte (NOTE: We're actually supposed to call it one Tebibyte ). Anyway, Modern, large-scale ICs can have hundreds of pins, so using 40 of them for physical address lines is not "an absurd number." \$\endgroup\$ Apr 29, 2018 at 19:04

1 Answer 1


The old 8086 couldn't address a TB of memory. That would have been absurd back then. Nowadays where memories are large, there are more address bits.

As for segmentation that refers to how instructions access a large memory. Let's say, for example, that you have a 4 GB memory. That means there are 32 hardware address lines. To address any arbitrary memory location from a instruction would require 32 address bits. That could be quite a burden to require all memory-addressing instructions to have.

One way to deal with this is segmentation. You might, for example, only encode 16 bits of address into instructions. The upper 16 bits would come from a special register for that purpose. To address any arbitrary location would require loading that segment register first. However, many operations are nearby in memory. A single segment register value could be used, for example, to address any of the few global variables accessed between subroutines.

Take a look at the instruction set of the early x86 processors. The very first ones had a limited fixed address space. Then as more memory became reasonable, various indirect reference registers were added. These were widened over time, and so were the number of bits directly encoded into instructions.

For a example from a different world, take a look at the original PIC 16 architecture. Those are microcontrollers, not the microprocessors you asked about, but the concept is the same. The first PIC 16 could address 128 bytes of RAM, and 7 bit addresses were included in instructions. As more memory became necessary, two unused bits of the STATUS register were used as upper address bits. Now any instruction could access any byte of the current 128 byte bank, with the bank defined by the two bank bits in STATUS. These machines could address 512 bytes of RAM.

The PIC 18 architecture extended this to 8 address bits per instruction, and a 4 bit bank register. This created 16 banks of 256 bytes each, for a total of 4096 bytes.

The tradeoff between the size of memory to be capable of addressing and the number of address bits spent per instruction has been with us for a long time. Pretty much every minicomputer from the 1960s to 1980s had some sort of banking scheme.

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    \$\begingroup\$ It is also interesting to note that a large part of the logical address space is not used for 'ordinary' memory interfacing; PCI/PCIe often has a very large address space in the logical address space, but this is never asserted to the usual A(n) pins. \$\endgroup\$ Apr 29, 2018 at 15:42

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