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For example,

always @(posedge clk)
begin
    repeat (20)
        @(posedge clk) ;
end

In this statement, when the clk is triggered at first time, repeat statement will be executed. However, if the clk is triggered next time, does it mean that there are two running repeat statements?

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1 Answer 1

4
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A 'posedge' (or other) condition only becomes effective (can be triggered again) if the events triggered by it have finished.

Thus the first posedge will start the repeat condition. After 20 "posedges" the one at the top can be triggered again.


A question popped up:
Yes, it is complete legal Verilog and can be used in test benches.

This is probably a more useful example:

always @(posedge signal)
begin 
   <do something>
   // ignore any posedges of signal for the next 20 clock cycles
   repeat (20)
      @(posedge clk);
end
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  • \$\begingroup\$ Thks! But, I have one more. Let's assume that the always block is triggered by posedge clk as well as other signals, if always block is triggered by posedge clk, then even though other signals come in while it is executing, then always block is not triggered until repeat (20) is finished? \$\endgroup\$ Apr 29, 2018 at 16:20
  • \$\begingroup\$ All the conditions in the always @(...) section are ineffective until the code triggered by one or more of them it has finished. \$\endgroup\$
    – Oldfart
    Apr 29, 2018 at 16:25
  • \$\begingroup\$ @sungjuncho correct. For simulation constructs like this, everything in the always block executes sequentially. Until it reaches the end, it will never start again - even if that causes it to miss events. \$\endgroup\$ Apr 29, 2018 at 16:26
  • \$\begingroup\$ this is bit late but what if I have always@(*) repeat (5) #a = 5 ; b = 4; # a= 4 ; b = 5; and in Testbench a = 4 and b = 5 initially \$\endgroup\$ May 29, 2023 at 10:32

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