8bit shift left register with serial in, serial out implementation in verilog

Question

I took an example from website that describes 8bit serial in serial out shift left register.

module shift (clk, si, so);
input        clk,si;
output       so;
reg    [7:0] tmp;
always @(posedge clk)
begin
   tmp    <= tmp << 1;
   tmp[0] <= si;
end
   assign so = tmp[7];
    endmodule

from above example, I think that this is strange implementation. This is because, inside always, when tmp[0] <= si; is executed first, then we will take unexpected output.

For example, let's assume si is 1, and when tmp is:

1010 1010

and, when tmp[0] <= si; is executed first(which will make an unexpected output), the output is:

0101 0110

But, if always statements are executed sequentially as it is written in above example, the output is

0101 0101

As a result, we cannot guarantee that the output could be what we expected.

Am I right? So, the correct implementation should be:

tmp <= (tmp << 1) + {7'b0000_000, si};

Or, can we prove that the above example is always executed sequentially?

Answer 1

HDL languages do not work like other computer languages. They all have what is called 'concurrent' assignments. Which means all assignments take place 'at the same time'.

Thus tmp[0] gets the value si at the same time as tmp[7:1] get the value from tmp[6:0].

Am I right?

No, I strongly suggest you study Verilog and VHDL in more detail.

---

I think I see where you are coming from. In Verilog when there are multiple concurrent assignments, the last one wins.

Thus tmp[0] gets assigned a zero: tmp <= tmp << 1;
Next it gets assigned si: tmp[0] <= si;
The last one overrides the previous.

I agree it is sloppy coding here.

However there are cases where using that technique greatly improves code readability. I always add a comment like this:

...
... // big complex FSM 
...
// Overrides all previous assignments above!     
if (emergency_stop)
   state <= FSM_IDLE;