I am starting to work on some designs with MCU-based boards, or sometimes just looking at companies' products involving MCUs such as Espressif, Udoo, NXP... I have noticed a puzzling similarity between those MCUs, be it ARM Cortex, PIC or AVR family processors: the power-supply pinout.

I have looked up topics about the benefits of having multiple Vdd and Vss pairs, but what i find disturbing is their immediate proximity, i.e. they are next to each other. While there should be little problem with reflow oven or wave soldering in assembling processes, when it comes to SMD hand soldering this gets quite tricky for assembly or repair. It is really easy to short Vdd and Vss with the latter method and unless visible or checked after assembly/repair, one might badly damage its MCU or power-supply and start the board's design anew in the worst case scenario.

Hence my question really is: are there some benefits or silicon chip design constraints to why such layout is common place on our beloved MCUs? I have little to zero knowledge about silicon chip design or manufacturing. Or is this a way to ease the placing and routing of bypass capacitors?

  • 1
    \$\begingroup\$ That's not a bug, it's a feature! \$\endgroup\$ Apr 30, 2018 at 23:17
  • \$\begingroup\$ A package is often much larger than the die, itself, which sits in a carrier and has wires that go between the wirebonds at the die and the package leads. It's usually best if the power leads are the shortest lead lengths. This is usually true for the pins in the center of the package. But often, this will be leads on opposite sides. Not immediately next to each other on the same side. \$\endgroup\$
    – jonk
    Apr 30, 2018 at 23:26

3 Answers 3


As you say, it is a complete non-issue for high-volume manufacturing, which is where the vast bulk of such chips goes — and those are the customers that the chip makers pay attention to. Hobbyists don't buy nearly enough chips for them to even notice.

But yes, there are real advantages to this arrangement, both on the chip and on the board. Power and ground are distributed on the chip in metal layers on top of the silicon, and these connections interfere the least with signal connections if they run parallel to each other to the greatest extent possible, and this includes the external contacts.

On the PCB, you get the best performance out of the decoupling capacitors if their connections are as short as possible, and putting the pins on the chip next to each other makes this much easier. It also helps avoid congestion with signal connections here, as well.

  • \$\begingroup\$ They used to be on diagonal corners of dips, (74XXX) which, at the time, made the pcb layout easier without requiring vias or even double sided pcbs. As the speed got higher, it became more important to get better bypassing, and all pcbs became 2+ layers with vias \$\endgroup\$
    – Henry Crun
    Apr 30, 2018 at 23:38
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    \$\begingroup\$ +1 Your third paragraph is the most important. The Vcc and Vdd pins are strategically selected at chip planning stage to provide most effective on-board bypass with SMT MLCC capacitors. Ancient-style diagonal placement has too much of trace inductance between pins and caps, so effective bypass of MCU-produced spikes is nearly impossible, especially when internal workings happen at GHz rates with edges on picosecond scale. \$\endgroup\$ Apr 30, 2018 at 23:49
  • \$\begingroup\$ Mutual inductance is a benefit of wiring Vdd and Vss in parallel. Digital power on the chip can ring a lot. Reducing the inductance to off-chip decoupling pushes the ringing down in amplitude and up in frequency. \$\endgroup\$
    – HKOB
    May 1, 2018 at 6:41

Are there some benefits or silicon chip design constraints to why such layout is common place on our beloved MCUs?

Major benefits. Each pair powers a subsection of the chip, you could say "one side" on a QFP. Each pair takes on a block of IO pins and peripherals.
For example on many chips Vdda takes care of the "sensitive part", the ADC and clocking. While the others are just "slow" GPIO and timers.
Some chips connect them all internally, some vendor measure each power pair with their peripherals during characterization, this way they can measure how much current each peripheral or only the core consumes. This means they are still separated internally.

The benefit of routing them outside next to each other is that you have the most effective decoupling. This is especially necessary in leaded chip where there is inductance in the package. (LQFP, SOIC, QFN). Less so for BGA and WLCSP, these move into an whole other level of power distribution. With planes and their impedances.

It is really easy to short Vdd and Vss with the latter method and unless visible or checked after assembly/repair

Just add flux. It's "magical" properties will easily prevent or remove bridges.
People often underestimate flux. Use a flux pen, or flux syringe.

Use a thermal camera when bringing the board live. If there is a power supply short, you will notice immediately.
For your own designs, just make sure your power supply is short-circuit proof.


Putting high-current pins like Vdd and Vss close together is essential for minimizing EM radiation. The current loop must be as small (narrow) as possible. Using the corner pins (7&14, 8&16) was a huge historic mistake.

Shorts are easily found with a millivolt meter. Just use a current-limited power supply, e.g. 1 A, and find your short where the highest Vss and lowest Vdd meet. I have seen this work even on low resistance ground planes and bus bars.


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