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I know that the dynamic power dissipation of a CMOS inverter is defined by the equation: Pd = (Cl)(Vdd^2)(fb). My teacher challenged us to find ways to reduce power dissipation besides the obvious ones (reduce bitrate, Vdd, etc.), and apparently the power dissipation is inversely proportional to the CMOS geometry. I'm assuming this is because changing the geometry will change the current through the MOSFET, but the current is proportional to W/L (where W is the gate width and L is the channel length). So if the power dissipation is inversely proportional, does that mean in relation to W or L?

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  • \$\begingroup\$ I believe that the Pd equation is missing the 1/2 coefficient. \$\endgroup\$ – Daniel May 1 '18 at 2:23
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You want to minimize the shoot-thru current during the time when both FETS are on. So make these FETS as weak as possible.

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  • \$\begingroup\$ Can this be achieved by reducing the gate width as much as possible, or is it more efficient to increase the gate length? \$\endgroup\$ – quaresmatic May 1 '18 at 18:15

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