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I followed with this tutorial into the end of it, but I got an error while trying to programming my DE2 altera kit.

the design is input pin output pin (pin_name1 and pin_name2) and an inverter instead of the circuit in the tutorial.

this is the pin mapping:

enter image description here

this is the warnings I get after compilation:

Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (306006): Found 1 output pins without output pin load capacitance assignment
    Info (306007): Pin "pin_name2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning (332068): No clocks defined in design.
Warning (332068): No clocks defined in design.
Warning (332068): No clocks defined in design.

this is the failure I got: enter image description here

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  • \$\begingroup\$ In my case, the 'Failed' message was caused by a mis-configured JTAG chain in the Programmer utility so I used a .CDF file from a sample/demo project for the board, changed the .CDF to reference my .POF and then it worked. \$\endgroup\$ – JimFred Sep 20 '18 at 15:51
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As Socrates says, this is a JTAG problem. Check signal integrity on the JTAG lines. Check the voltage level and especially the clock. If there is ringing during the rise of the clock, it will try to clock in 2 bits instead of one. This will cause JTAG to fail.

Regarding the warnings:

Warning (20028): Parallel compilation is not licensed and has been disabled

means it Quratus II using one core. It will not take long for such a simple design

Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground' This means don't connect other chips to other pins.

Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.

This isn't necessary for a small design. It is useful for large designs and partial recompilation.

Warning (306006): Found 1 output pins without output pin load capacitance assignment Info (306007): Pin "pin_name2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis

This means the reported timing will be faster than it really is.

Warning (332068): No clocks defined in design.

That makes sense; you don't have any clocked registers.

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The problem is with programmer link, not the design itself. Check all the required connections. Why not to try the design using JTAG to FPGA instead of programming the memory device?

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