# How can I implement this function with JK Flip Flop + NAND Gates

I have a problem about logic design. I need to design MOD 5 Up/Down Counter with control input x, when x=0 it will count down and when x=1 it will count up. I'm allowed to use only JK flip flop and NAND Gate. Complement of x is not available. I thought a 3-bit number which is ABC. I wrote the table and I created a Karnough map for A which is the first digit. But, I am stuck in here because the function I got for A is (A'.B'.C'.x'+B.C.x) and I couldn't find any way to implement this function with given gates. The final step must be in JK Flip Flop to make it synchronized with the clock. I'm thinking for 2 hours about this. Can you give me a way to implement this function? Thanks in advance... Note: Complements of A, B, C are available and Logic Levels 1 and 0 are available.

• One NAND gate? – Eugene Sh. May 1 '18 at 18:44
• no, multiple nand gates and jk flip flops can be used. – orkundagci May 1 '18 at 18:47
• Well, just with NAND gates you can implement anything. NAND gates are functionally complete. Can you think how you implement NOT with NAND? Hint: Not(A)=NAND(A,A). – Eugene Sh. May 1 '18 at 18:50

As a general rule the following is true..

1) U' = U NAND U

This can be built from one NAND gate.

2) U OR V = U' NAND V' = (U NAND U) NAND (V NAND V)

This can be built from two 2-input NAND gates.

3) U AND V = (U NAND V)' = (U NAND V) NAND (U NAND V)

This can be built from two 2-input NAND gates.

We can apply the above rules over and ove to the equation below.

(A'.B'.C'.x'+B.C.x)

A' = A NAND A
B' = B NAND B
C' = C NAND C
X' = X NAND X

D = A' NAND B' (intermediate signal)
E = C' NAND X' (intermediate signal)

D' = D NAND D (which is A'.B')
E' = E NAND E (which is C'.x')

F = D' NAND E' (intermediate signal)
F' = F NAND F (which is A'.B'.C'.x')

G = B NAND C (intermediate signal)
G' = G NAND G (which is B.C)
H = G' NAND X (intermediate signal)
H' = H NAND H (which is B.C.x)

I = F NAND H (which is A'.B'.C'.x'+B.C.x)

Expanding the whole thing gives...

A'.B'.C'.x'+B.C.x = F NAND H

A'.B'.C'.x'+B.C.x = (D' NAND E') NAND (G' NAND X)

A'.B'.C'.x'+B.C.x = ((D NAND D) NAND (E NAND E)) NAND ((G NAND G) NAND X)

A'.B'.C'.x'+B.C.x = (((A' NAND B') NAND (A' NAND B')) NAND ((C' NAND X') NAND (C' NAND X'))) NAND (((B NAND C) NAND (B NAND C)) NAND X)

A'.B'.C'.x'+B.C.x = ((((A NAND A) NAND (B NAND B)) NAND ((A NAND A) NAND (B NAND B))) NAND (((C NAND C) NAND (X NAND X)) NAND ((C NAND C) NAND (X NAND X)))) NAND (((B NAND C) NAND (B NAND C)) NAND X) simulate this circuit – Schematic created using CircuitLab

• I don't feel like editing your answer lol... but if you're just curious for next time, try utilizing the \cdot $\cdot$ for AND and \overline{X} $\overline{X}$ to negate something. I wouldn't blame you for adding all of the Mathjax for this... – KingDuken May 1 '18 at 20:19