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I need to design a mod-5 up/down counter with control input x. When x = 0 it will count down, and when x = 1 it will count up. I'm allowed to use only a JK flip-flop and NAND gates. Complement of x is not available.

I thought a 3-bit number which is ABC. I wrote the table and I created a Karnaugh map for A which is the first digit. I am stuck there because the function I got for A is (A'.B'.C'.x'+B.C.x) and I couldn't find any way to implement this function with the given gates.

The final step must be in the JK flip-flop to make it synchronize with the clock.

I have been thinking for two hours about this. Can you give me a way to implement this function?

Note: Complements of A, B, and C are available and logic levels 1 and 0 are available.

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  • \$\begingroup\$ One NAND gate? \$\endgroup\$
    – Eugene Sh.
    May 1, 2018 at 18:44
  • \$\begingroup\$ no, multiple nand gates and jk flip flops can be used. \$\endgroup\$
    – orkundagci
    May 1, 2018 at 18:47
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    \$\begingroup\$ Well, just with NAND gates you can implement anything. NAND gates are functionally complete. Can you think how you implement NOT with NAND? Hint: Not(A)=NAND(A,A). \$\endgroup\$
    – Eugene Sh.
    May 1, 2018 at 18:50
  • \$\begingroup\$ Hint:Moore state machine \$\endgroup\$
    – Miss Mulan
    Jul 1, 2022 at 22:40

1 Answer 1

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As a general rule the following is true..

1) U' = U NAND U

This can be built from one NAND gate.

2) U OR V = U' NAND V' = (U NAND U) NAND (V NAND V)

This can be built from two 2-input NAND gates.

3) U AND V = (U NAND V)' = (U NAND V) NAND (U NAND V)

This can be built from two 2-input NAND gates.



We can apply the above rules over and ove to the equation below.

(A'.B'.C'.x'+B.C.x)

A' = A NAND A
B' = B NAND B
C' = C NAND C
X' = X NAND X

D = A' NAND B' (intermediate signal)
E = C' NAND X' (intermediate signal)

D' = D NAND D (which is A'.B')
E' = E NAND E (which is C'.x')

F = D' NAND E' (intermediate signal)
F' = F NAND F (which is A'.B'.C'.x')

G = B NAND C (intermediate signal)
G' = G NAND G (which is B.C)
H = G' NAND X (intermediate signal)
H' = H NAND H (which is B.C.x)

I = F NAND H (which is A'.B'.C'.x'+B.C.x)

Expanding the whole thing gives...

A'.B'.C'.x'+B.C.x = F NAND H

A'.B'.C'.x'+B.C.x = (D' NAND E') NAND (G' NAND X)

A'.B'.C'.x'+B.C.x = ((D NAND D) NAND (E NAND E)) NAND ((G NAND G) NAND X)

A'.B'.C'.x'+B.C.x = (((A' NAND B') NAND (A' NAND B')) NAND ((C' NAND X') NAND (C' NAND X'))) NAND (((B NAND C) NAND (B NAND C)) NAND X)

A'.B'.C'.x'+B.C.x = ((((A NAND A) NAND (B NAND B)) NAND ((A NAND A) NAND (B NAND B))) NAND (((C NAND C) NAND (X NAND X)) NAND ((C NAND C) NAND (X NAND X)))) NAND (((B NAND C) NAND (B NAND C)) NAND X)

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ I don't feel like editing your answer lol... but if you're just curious for next time, try utilizing the \cdot \$\cdot\$ for AND and \overline{X} \$\overline{X}\$ to negate something. I wouldn't blame you for adding all of the Mathjax for this... \$\endgroup\$
    – user103380
    May 1, 2018 at 20:19

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