I need to design an LDO regulator that only sources supply voltage and current to the load whenever it receives a logic-1 signal. Since the main element used in the LDO regulator is a differential amplifier, I would like to know how I can take the standard two-stage op-amp design and attach an Enable pin to it so that it works as I've described. See the image below for the CMOS op-amp I'm using.

enter image description here

I had a difficult time trying to word this question, so please let me know if more details are required.

  • \$\begingroup\$ Another important element of an LDO is the pass transistor. Consider how the op-amp is connected to the pass transistor, and how you might change that to disable the regulator. \$\endgroup\$ – The Photon May 2 '18 at 4:22
  • \$\begingroup\$ I believe you could do the trick with 2 PMOS: one with its source on VDD (to cut the power supply) and the other with source on Vout (to enable load). They would enable with logic 0, so you should place an inverter before the signal. Just some ideas to consider. \$\endgroup\$ – Vicente Cunha May 2 '18 at 4:27
  • \$\begingroup\$ Maybe start by killing the bias and see if anything else is required. \$\endgroup\$ – Spehro Pefhany May 2 '18 at 4:39
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    \$\begingroup\$ Best is to start with posting a diagram of the whole regulator. By the way there are plenty of regulators with an enable pin. \$\endgroup\$ – Oldfart May 2 '18 at 5:18

To add power down functionality to the op-amp above you need to cut the current flow. You can do this by adding transistors acting as pull-up, pull-down and switches. These are typically controlled with digital signals and it could be good to buffer the control signals using the local supply voltages to reduce supply and cross-talk noise. Pull-ups and pull-downs can often be near minimum size (unless slow timing causes excess leakage or short-circuit currents that are seen as problematic), while switches may need a lower on-resistance.

To cut the current in the op-amp you have shown, you can do this:

  • Pull up the gate of M7 high using a PMOS
  • Pull down Vbias3 and/or Vbias4
  • Do one of the following:
    • Add a switch (NMOS or transmission gate depending on the voltage level) to the input of the Vbias input you are pulling down.
    • Cut the power in the circuit that is generating the Vbias you are pulling down (if you only have one such circuit it might be best to cut power in both).

For the complete LDO you also need to handle the other branches that might leak. The most important thing to do is to :

  • Pull up (or down) the LDO output transistor so it turns off.

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