# How to avoid writing to and reading from 2D array at the same time vhdl

Hi for something I work on, I must use an 2D array but I find it dangerious to write to and read from a certain memory location in the array at the same time. How can I control this situation? When both reading and writing is necessary at the same time, I want to prioritize writing and instead of reading from that certain location, The old value should be kept in the signal to which I read from array and write. My narrating could be complicating. I am sorry for that.

You are anxious not to tell us what you are working on. Also you do not tell us if this is ASIC or FPGA nor how big the memory is.

FPGA vendors have ready-made dual-ported memories where you can set the operating mode. They all offer three modes:

For small memories you can write your own but this website does not provide 'please write my code for me' service. You should try first and when you get stuck show us the code and where it goes wrong, then we can help you.

As last remark: I am not sure you need that behavior, mostly the read-old, write-new behavior is what is required. Alternative you find that read-write clashes doe not happen (FIFO) or double buffering is required. (e.g. BCH and FFT)

Reading and writing from the same memory position simultaneously is actually not a problem. If you use a dual port RAM this is exactly what you're doing.

architecture rtl of dpram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;

begin
process (clk)
-- Write memory.
begin
if (rising_edge(clk) then
if (write_en = '1') then
end if;
end if;
end process;