I want to run a number of sensors up the length of a flex circuit, they all communicate via SPI and I will run chip selects individually to each device.

I need the flex circuit width to be minimal so its likely I will have tracks in close proximity running the entire length of the flex circuit.

Im concerned with how this will affect the SPI comms with increasing length.

EDIT: The SPI will run at a maximum speed of 1MHz, data will be active on both MOSI and MISO, One mircoprocessor will sit at one end of the flex circuit as master, comunnicating with the chain of sensors.

I'm not looking for an exact figure just ball park, so that i can decide o na length to test with first. This answer SPI max distance gives the max length for cables, but i think that this is not applicable to that of a flex circuit.

How long can I go with the SPI on a flex circuit?

  • \$\begingroup\$ What clock frequency? What velocity of propagation of flex circuit? Are you driving in one direction master to slave or using bi directional communications? \$\endgroup\$ – Andy aka May 3 '18 at 9:28
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    \$\begingroup\$ There is no simple answer to your question. Adding length to the traces causes additional trace capacitance, resistance and inductance. The longer traces can also be coupled with other nearby signals with fast edges. The max length will depend on the data rate, operating voltage, load capacitance, driver source impedance and other nearby fast tracks. You can probably go just about as far on flex as you can on rigid pcb material if that helps (assuming no ground plane under the traces). \$\endgroup\$ – Dean Franks May 3 '18 at 9:29
  • \$\begingroup\$ @Andyaka thanks for suggestion on clarity have updated to include some of your points. However velocity of propogation of flex, you've lost me here \$\endgroup\$ – Pop24 May 3 '18 at 10:26
  • \$\begingroup\$ @DeanFranks unfortunately i have no experience in routing SPI over a considerable distance on PCB, what sort of figure would you suggest for a Rigid PCB? \$\endgroup\$ – Pop24 May 3 '18 at 10:27
  • \$\begingroup\$ @DeanFranks, if you want to minimize the coupling between the traces, you definitely want to have a ground plane. The spacing to the ground plane should be much closer than the spacing between the traces to minimize the coupling between the traces. Without a ground plane, you could run grounds between the traces to isolate them, i.e. "ground-signal-ground" routing. \$\endgroup\$ – crj11 May 3 '18 at 10:46

A bi-directional SPI bus (master -> slave -> master) is the most problematic to deal with. Consider the much simpler master to slave comms - both data and clock remain in time-sync on their route to the slave.

However, when the slave transmits back to the master it does so by syncing to the delayed clock it receives from the master. That delay is due to the propagation time through the channel (cable, PCB etc..). Then there is the extra delay of the data coming back i.e. two lots of propagation delay and the master might end up trying to receive data that has shifted a significant part of one clock cycle.

With a 1 MHz clock, the period is 1000 ns and if the received data from the slave has shifted more than about a quarter of this time (250 ns) then expect problems.

The velocity of propagation of free space is 300,000,000 m/s or, put differently, 3.333 ns per metre. Cable may double this figure and I wouldn't expect this to be any worse for a PCB so assuming a worst case of 7 ns per metre, you could run 250/7 metres and not hit delay problems. That's nearly a 36 metre round trip or 18 metres of cable.

I'm not saying that signal levels will be totally adequate after 18 metres but that 18 metres should not produce a show-stopping round-trip delay.

There are also reflections to consider and the rule of thumb is that they become significant if the cable length approaches one-tenth of the wavelength of the highest relevant frequency. What frequency you might ask? Well the clock is 1 MHz and it contains harmonics that are usually regarded as important up the the seventh so, the frequency in question is 7 MHz. This has a wavelength in free space of about 43 metres and if run in a "slow" cable this might be 20 metres.

For this reason (and the one-tenth rule of thumb) I wouldn't want to go further than 2 metres without paying some attention to line terminators. They can be added to SPI lines without too much difficulty but, if you don't want them then I'd say 2 metres is your limit.

  • \$\begingroup\$ Brilliant answer, really appreciate the detail, and running through exactly what it is that is having an affect on the comms and how each contributes to the degradation of the signal. thanks very much! \$\endgroup\$ – Pop24 May 3 '18 at 11:01
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    \$\begingroup\$ Keep in mind that for signal integrity edge rates also matter, not just clock periods and propagation delays. A rule of thumb is that the signal bandwidth in GHz in 0.35 over the rise time in ns. For example, for a 5ns rise time, you have a 70MHz signal bandwidth. \$\endgroup\$ – crj11 May 3 '18 at 12:48
  • \$\begingroup\$ @crj11 in my answer I used the formula 7 x basic clock rate as a measure for predicting the maximum frequency. \$\endgroup\$ – Andy aka May 3 '18 at 13:53

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