For process statements in VHDL, it is said that the order of execution is sequential. My question is, are the signals
c assigned to their new values concurrently, or sequentially?
process(clk) is begin if rising_edge(clk) then a <= b; b <= c; c <= a; a <= c; end if; end process;
If this is sequential, I must say that after the end of the process,
a is equal to
b is equal to
c is equal to
b, because we assigned
a before we assigned
a must be
c is assigned to
b before last signal assignment. However, this does seem impossible to implement in hardware.