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For process statements in VHDL, it is said that the order of execution is sequential. My question is, are the signals a, b, and c assigned to their new values concurrently, or sequentially?

process(clk) is
begin
    if rising_edge(clk) then
        a <= b;
        b <= c;
        c <= a;
        a <= c;
    end if;
end process;

If this is sequential, I must say that after the end of the process, a is equal to b, b is equal to c, and c is equal to b, because we assigned b to a before we assigned a to c.

And finally a must be b, because c is assigned to b before last signal assignment. However, this does seem impossible to implement in hardware.

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Within a process, statements are indeed carried out sequentially. However, values assigned to signals are not carried out immediately but scheduled to occur at the end of the process.

For example, when your third assignment c <= a; is carried out, the value of a is still the value a had at the start of the process.

This is because the first assignment a <= b; has not yet been carried out and a has not changed.

In fact, the first assignment will never be carried out because of the fourth assignment a <= c;, which will be scheduled to occur at the process end instead.

This behaviour reflects the behaviour of real logic circuitry, which is what VHDL was designed to do.

I recommend you read up on how VHDL processes work. Make sure you avoid a classic HDL trap: seeing a Hardware Design Language that models a logic circuit as a computer program that is executed by a CPU.

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  • \$\begingroup\$ I believe the compiler should warn or throw an error about multiple drivers for a. \$\endgroup\$ – Eugene Sh. May 3 '18 at 16:04
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    \$\begingroup\$ @EugeneSh., no, there's only one driver for 'a', that process. It contains multiple assignments to 'a', which is perfectly legal and commonplace in a process e.g. a<='1'; if b then a<='0'; end if; \$\endgroup\$ – TonyM May 3 '18 at 16:06
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It often helps to look at the RTL schematic. Your code:

process(clk) is
begin
    if rising_edge(clk) then
        a <= b;
        b <= c;
        c <= a;
        a <= c;
    end if;
end process;

yields this:

RTL

Reading your statements in reverse order:

  • a <= c -- the a register gets whatever was in the c register
  • c <= a -- the c register gets whatever was in the a register
  • b <= c -- the b register gets whatever was in the c register
  • a <= b -- this statement is ignored1.

1There can't be two drivers for a single FF input so, in VHDL, when multiple assignments to a signal occur within the same process statement, the last assigned value is the value which is propagated.

Notice also that b_reg and a_reg are exactly the same (i.e. they each clock the same signal in and out). If this simple example were to be synthesized, one of them would almost certainly be removed, and bout would be tied to aout. In fact, it took some keep attributes just to tell Vivado to not eliminate the b_reg for the RTL.

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In VHDL, statements in process execute sequentially. As you mentioned a, b, c and d are signals (if they were variables, they had different manner). assume these statements in process:

a <= b;
c <= a;

At the end of the process old value of b assigned to a. and old value of a assigned to c.

we can think in simpler way: statements in process executed sequentially, but the signals don't get the new values before end of the process. see this example that simulated in vivado:

simulation

you can see the initial value of the signal before rising edge of clock.

a=1; b=1; c=0;

In the rising edge of clock, the statements in the process executed. so at the end of process the new value of signals (according to assignment operations given in the question) are:

a=old c=0;

b=old c=0;

c=old a=1;

good luck.

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