0
\$\begingroup\$

Hi I am writing a code for image processing that includes a Ram to/from which data will be written and read. However, I am getting 15 errors like the one below.

[DRC MDRV-1] Multiple Driver Nets: Net address_ram[10] has multiple drivers: 
address_ram_reg[10]/Q, and address_ram_reg[10]__0/Q.

I created this ram by using block ram generator in Vivado 2017.2. It is single port ram and initialized with some .coe file. My knowledge on rams is limited. What I know or what I strongly assume to be true is that when write_enable is 1, data will be written to the location described by the address_ram. Does not matter if write_enable is 1, data will be read from the location described by the address_ram. By the way, ram is always enabled.

Here what I have

I read in rising edge of the clock and write in falling edge of the clock in order to avoid some clashing.

Reading_from_Ram: process(clk) is
begin
if rising_edge(clk) then
if (pos_x < PICTURE_WIDTH_HEIGHT) and (pos_y <PICTURE_WIDTH_HEIGHT) and 
(pos_x >= 0) and (pos_y >= 0) then
address_ram <= (conv_std_logic_vector((pos_x + 
pos_y*PICTURE_WIDTH_HEIGHT),16));
end if;
end if;
end process;

Writing_to_Ram: process(clk) is
begin
if falling_edge(clk) then
if (pos_x < PICTURE_WIDTH_HEIGHT) and (pos_y <PICTURE_WIDTH_HEIGHT) and 
(pos_x 
>= 0) and (pos_y >= 0) then
write_enable <= '1';
address_ram <= (conv_std_logic_vector((pos_x + 
pos_y*PICTURE_WIDTH_HEIGHT),16));
end if;
write_enable <= '0';
end if;
end process;

U4: Block_Ram port map(addra => address_ram,
                       clka => clk,
                       dina => data_in_ram,
                       douta => data_out_ram,
                       wea => write_enable);

data_out_ram and data_in_ram are used in changing brigtness and contrast.

U5: Brightness_Contrast port map(clk_in => clk,
                                 operation => operation,
                                 pos_x => pos_x,
                                 pos_y => pos_y,
                                 data_in => data_out_ram,
                                 cursor_pos_x => cursor_pos_x,
                                 cursor_pos_y => cursor_pos_y,
                                 length => length,
                                 output_of_operation => data_in_ram,
                                 mode => mode);

This is all I can say. How can I get rid of these errors??

edit:

Reading_Writing_Ram: process(clk) is
begin
if rising_edge(clk) then
if (pos_x < PICTURE_WIDTH_HEIGHT) and (pos_y <PICTURE_WIDTH_HEIGHT) and 
(pos_x >= 0) and (pos_y >= 0) then -- if within picture
address_ram <=(conv_std_logic_vector((pos_x + 
pos_y*PICTURE_WIDTH_HEIGHT),16));
if ( pos_x > cursor_pos_x - 1) and (pos_x < cursor_pos_x + length) and ( 
pos_y > cursor_pos_y - 1) and (pos_y < cursor_pos_y + length) then --if 
within cursor
write_enable <= '1';
else
write_enable <= '0';
end if;
end if;
end if;
end process;

I rewrote it again(code above) and solved the problem. Thanks everyone who helped

\$\endgroup\$
  • \$\begingroup\$ The error message tells you exactly what's wrong : you are driving the address from more than one process. (As they are both driving it with the same computed value at the same time, you got lucky; simply comment one of them out) \$\endgroup\$ – Brian Drummond May 3 '18 at 19:37
  • \$\begingroup\$ Also check your write_enable. I think it will always be zero. (but your code indent format is obfuscating a good analysis). \$\endgroup\$ – Oldfart May 3 '18 at 19:44
0
\$\begingroup\$

You are writing address_ram from two separate processes. Just put them in the same process and it should work fine.

As a general note, when you multiply assign a signal in a process, the last assignment in the process overrides all of the previous assignments. In many cases this is used to set a default value for a signal that is changed later in the process.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.