# Bus tapping in Xilinx ISE for 8 bit to 16 bit conversion

I have a processing unit which is controlled by a sequencer/control unit. The agenda of this processing unit is to multiply 2 numbers using 8 BIT registers using the bit shift and add method.

Once the registers propagate the data in them to the 16 bit adder, I have to convert the 8 BIT values to 16 bits.

The input bus has to be 8 bits wide and the bus widths have to be set in the ISE schematic creator. I'm having issues trying to understand the need for bus tapping and how to use it to create a 16BIT to 8 BIT converter.

My questions:

1. How do I get the bus widths rite? Conversion?
2. How do I extract the LSB from the REG SR8CLED?

You need an 8 bit register to store half of your 16 bit word. Store the 8 bits that are transferred on the first cycle, then pass the 8 bits transferred on the next cycle straight through to the adder.

• But the shift registers propagate only 8 bit but what comes off the adder is 16 bits. Are you saying use an 8 bit adder instead? Commented May 4, 2018 at 12:22
• No, you would concatenate the bus with the output of the register to get 16 bits. Commented May 4, 2018 at 13:37
• Unless I am misunderstanding what you are trying to do. If you are only taking an 8 bit input, then maybe you need to sign extend or zero extend it to 16 bits. Commented May 4, 2018 at 13:38

How you extend an 8-bit value to 16 bits depends on what the bits represent.

• If they represent an unsigned quantity, you simply prepend 8 zeros:

11001011 → 00000000 11001011 (both of these represent 203)

• If they represent a 2's-complement signed number, where the MSB is the sign bit, you need to prepend 8 additional copies of the sign bit:

11001011 → 11111111 11001011 (both of these represent -53)

01001011 → 00000000 01001011 (both of these represent +75)

• Yes i am aware of that, but I wanted to know how this can be realized in Xilinx, I've been trying some online content but none of them could explain the intricate process of realizing it. My second picture has an incomplete schematic of the converter using wire method. Commented May 4, 2018 at 14:25
• So 90% of your question is irrelevant -- you simply don't know how to use Xilinx bus taps? Have you read the documentation? I can't help you there; I do all of my FPGA programming in HDL. Commented May 4, 2018 at 15:57