I have designed a high precision frequency counter circuit. I am using it to measure a frequency of around 35kHz that is stable to 0.1mHz. I can measure the frequency using a Stanford Research Systems SR620 and the only digits that change are 0.000XXX. My frequency counter varies by about 1Hz with the same signal. The SR620 uses some sort of Mean calculation to provide a more precise result. I am looking to learn how to do the same.
How the circuit works
There are two counters. A count down counter and a count up counter. The count down counter is loaded with the base frequency (or expected perfect input frequency) multiplied by the sample time in seconds. The count down counter decrements on each period of the 35kHz input. The count up counter counts a 2GHz signal while the count down is counting to zero. The count up counter stops when the count down counter reaches zero.
Then frequency = (base frequency * sample time in seconds) / (count up counter / 2GHz) or (count down counter start count) / (count up counter / 2GHz)
My circuit uses a PLL chip locked to a 10ppb 100MHz OCXO to generate a 2GHz signal. Using a rubidium standards 1pps output my counter is accurate to 2,000,000,000 +-15 for a 1 second reading. I need to be able to read a 35kHz signal and be accurate to 100uHz for a 1 second reading. The 35kHz signal can vary to as low as 31kHz and to as high as 39kHz but my readings are not performed while the frequency is changing.
What kind of calculation would make these readings more accurate and does anyone know of a resource that explains it?
My issue ended up being a circuit logic to software issue. My standard deviation went from 1Hz to 100uHz after the fix. I did not need to modify my firmware math.