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I have designed a high precision frequency counter circuit. I am using it to measure a frequency of around 35kHz that is stable to 0.1mHz. I can measure the frequency using a Stanford Research Systems SR620 and the only digits that change are 0.000XXX. My frequency counter varies by about 1Hz with the same signal. The SR620 uses some sort of Mean calculation to provide a more precise result. I am looking to learn how to do the same.

How the circuit works

There are two counters. A count down counter and a count up counter. The count down counter is loaded with the base frequency (or expected perfect input frequency) multiplied by the sample time in seconds. The count down counter decrements on each period of the 35kHz input. The count up counter counts a 2GHz signal while the count down is counting to zero. The count up counter stops when the count down counter reaches zero.

Then frequency = (base frequency * sample time in seconds) / (count up counter / 2GHz) or (count down counter start count) / (count up counter / 2GHz)

My circuit uses a PLL chip locked to a 10ppb 100MHz OCXO to generate a 2GHz signal. Using a rubidium standards 1pps output my counter is accurate to 2,000,000,000 +-15 for a 1 second reading. I need to be able to read a 35kHz signal and be accurate to 100uHz for a 1 second reading. The 35kHz signal can vary to as low as 31kHz and to as high as 39kHz but my readings are not performed while the frequency is changing.

What kind of calculation would make these readings more accurate and does anyone know of a resource that explains it?

My Solution

My issue ended up being a circuit logic to software issue. My standard deviation went from 1Hz to 100uHz after the fix. I did not need to modify my firmware math.

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    \$\begingroup\$ Finally! A correct use of the unit "mHz"! \$\endgroup\$ – Dave Tweed May 4 '18 at 18:01
  • \$\begingroup\$ The SR620 manual and application note give a lot of detail. Impressive list of parts, but no schematic or block diagram. Includes a Z80 processor, so a lot can be done in firmware. \$\endgroup\$ – Dave Tweed May 4 '18 at 18:14
  • \$\begingroup\$ @DaveTweed Actually, the paper version of the SR620 includes also the schematic. \$\endgroup\$ – Massimo Ortolano May 4 '18 at 18:16
  • \$\begingroup\$ From the equation you posted, it doesn't seem you've implemented a reciprocal counter. \$\endgroup\$ – Massimo Ortolano May 4 '18 at 18:18
  • \$\begingroup\$ How much does the frequency vary? What is the range of values? How often does it change? How closely do you know the frequency? \$\endgroup\$ – Henry Crun May 4 '18 at 18:47
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A plain reciprocal counter should give F-Clock/T-Measurement resolution. i.e 0.0035Hz/second with 10MHz clock. A pic/avr should achieve this by simple reciprocal counting with its timer capture registers.

That is what you should be achieving.

Your measurements must be coherent for accuracy to increase linearly i.e. the capture counter must be running continuously to count N through M multiple edges of the input signal. If you average incoherent measurements, accuracy only increases by sqrt()


they long ago used an analog interpolator {linear ramp and samplers) to go between the clock resolution e,g to add 3 digits resolution eg 100M clock =11 digits/second

For stable or almost known frequencies, you can mix down then measure period of the beat frequency. this increases resolution dramatically in fact right to the phase noise/allen variance limit of the clock source, even just using an ordinary uP as the counter

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I don't know how the SR620 does it, but this is how I suggest doing it.

Suppose you want at least 10 readings per second. Divide the 35000+/- frequency by about 3500. Maybe you pick 4096 or 2048, say the latter. That gives you an edge every 58.514285714 ms, dividing by 2^n where n = 11.

Use that with a reasonable clock, say Fosc = 25MHz. You will have 1462857 clocks per cycle, giving you solid 6-digit resolution at 17Hz sample rate. If you need more resolution, increase n or Fosc. If you increase n you reduce the sample rate, of course. If you increase Fosc the logic has to work faster and the sharpness of the edges on your 35kHz becomes more important.

To get the measured frequency F from the number of clocks k,

F =\$\frac{F_{OSC}\cdot 2^n}{k}\$


I see you've added the clock frequency to your question- at 2GHz, the edges of the input signal have to be very sharp, the comparator very fast, the reference voltage and signal amplitude very stable etc. to get full benefit from the high clock frequency.

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  • \$\begingroup\$ Yes the PLL outputs a differential 2GHz signal that is read with an 8-bit ECL logic ripple counter that is good to I believe 2.4GHz. When the ripple counter overflows, it increments a lower speed 32-bit counter. \$\endgroup\$ – ozziwald May 4 '18 at 20:59
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Given a stable time base, a desired readout interval equal to N cycles of that time base, and a stable input signal whose frequency is equal to at least twice the readout frequency, one may relatively easily measure the frequency with an uncertainty fraction of 3/N.

Each time an input pulse occurs, sample the time and the number of pulses that have occurred to date. At each readout interval, capture the sampled time and count values. Divide the difference in counts by the difference in time, and that will be the frequency. For any signal whose frequency is greater than some integer K times the readout frequency, the interval being measured will be at least (K-1)/(K+1) of the readout interval. In the worst case where the input frequency is just below 3x the readout frequency, the interval will be just over 1/3 the readout period.

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Here is an Arxiv paper that should be helpful. It gives an overview of precision frequency measurement and then proposes a new improved statistical based measurement method.

From the paper:

Higher resolution is obtained by measuring fractions of the clock period with a suitable interpolator. Simple and precise interpolators work only at fixed frequency. The most widely used techniques are described underneath. Surprisingly, all them are rather old and feature picosecond range resolution.

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HP used analog charge-storage interpolation in a reciprocal time-pulse counter beast in the 1960s.. The transistors were 2N5179.

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