I have an ALU module with a set of parameters used as opcodes.

         parameter ADD=0,
         SUB = 1,
         MUL = 2,
         DIV = 3;

Currently building a testbench for that module, I just want to read these values in the testbench, something like C language alu.ADD .

Is that possible ?

  • \$\begingroup\$ Have you tried simply instanceName.ADD? \$\endgroup\$ May 4, 2018 at 22:37

1 Answer 1


You can access any variable within a hierarchy, including parameters, in Verilog testbenches pretty much exactly as you have shown.


Say you instantiated your module and called the instance alu, then you could access the value of the parameter ADD in that instance by simply accessing:


You can even do multi-level. Say your alu instance instantiated something called adder, which had a signal called cout. You could access that with:

  • \$\begingroup\$ I tried that before and didn't work !! I use iverilog and when it fails it prints I gave up I've just tried it now and it worked... \$\endgroup\$
    – Shady Atef
    May 4, 2018 at 22:49

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