I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies won't cause any hazards.

So i was wondering if there exists processors with hazards because of this WAW and WAR dependency?

If there are, please can you name some of them. Thank you! (I searched google but found nothing useful)

  • 1
    \$\begingroup\$ Since you've been studying architectures and pipelines, I assume you understand why there is a potential hazard with read-after-write. That's trivially easy to explain if there is a pipeline. So, knowing that, tell me what design arrangement in a single cycle pipelined architecture is required in order to create a write-after-write hazard or a write-after-read hazard. If you can answer that, you may have your answer. Easily answered, if some instructions execute faster than others. But keep in mind this one important fact you mentioned: single cycle architecture. \$\endgroup\$ – jonk May 5 '18 at 5:16
  • \$\begingroup\$ so what are the names? \$\endgroup\$ – Moeinh77 May 6 '18 at 2:09
  • \$\begingroup\$ I'll provide a greatly narrowing hint. Search through the set of \$k\$-way superscalar, single-cycle processors. (The bold part is your requirement.) \$\endgroup\$ – jonk May 6 '18 at 4:45

All pipelined processors are susceptible to this. There's a particularly good technote on resolving this on the SPARC due to the pipeline and local register windowing with functions.

1: add $1, $2, $3 ;writes to $1
2: mul $4, $1, $5 ;reads from $1

In the code above, the Read-After-Write hazard exists as 2 reads $1 before the writeback. If you have pipeline of any depth.

Write-After-Read and Write-After-Write dependencies do not cause pipeline hazards.


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