What is $V_{ADJ}^{+}$ and $V_{ADJ}^{-}$ for this adjustable delay schematic?

Here is the adjustable delay schematic,and as i know,the $V_{ADJ}^{+}$ and $V_{ADJ}^{-}$ is off chip for testing ﬂexibility.

But i'm curious that the delay is for the time delay,why should we feed the voltage to it?If we don't feed voltage to $V_{ADJ}^{+}$ and $V_{ADJ}^{-}$,is this schematic still a delay schematic?but if we don't feed it,where should i connect the gate of $M_{PGm}$ and $M_{NGm}$ to?

blue wave is $V_{DLY}$,output.Red line is $V_{CP_PK}$,input.

$V_{ADJ}^{+}$ connect ground,and $V_{ADJ}^{-}$ connect $V_{DD}$

The upper and lower MOSFETs in conjuntion with their respective 200 kohm resistors act like current sources. The voltages on their respective gates make the current they can provide higher or lower. So when one or the other middle MOSFETs activate, one or the other outer MOSFETs delivers current to charge up (or down) C$_{ADJ}$ and the current forms a ramping voltage.

If that current is variable then the ramp can be made quicker or slower thus it takes less or more time for the output MOSFETs to switch.

If you want a fast rate then connect -V$_{ADJ}$ to Vdd and +V$_{ADJ}$ to ground. If you want a slow rate then connect them both to midrail.

• oh,so that two $V_{adj}$ just control the rise time and fall time of output's.Where is the midrail,i don't understand it? – XM551 May 5 '18 at 8:27
• Mid rail is a voltage half way between Vdd and circuit 0 volts. – Andy aka May 5 '18 at 8:44
• The output is still square in nature but the input voltage to the output MOSFETs is ramping. – Andy aka May 5 '18 at 8:45
• I test it and i think this schematic just let some wave become more similar to square wave,i thought the delay schematic is let the wave shift some second – XM551 May 6 '18 at 6:01
• In the added picture to your question, why have you fed the input (red) with such a strange waveform? With those values in the circuit, t will not be very much (a few hundred nano seconds). – Andy aka May 6 '18 at 8:08