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What is the maximum number of opcodes for the question, the answer is c option, but i think it is option d, because, each address specifies each memory location, there are 16 address lines, which means 2^16 addresses i.e., 2^16 memory locations.

So, if each location contains one opcode, total 2^16 locations contain 2^16 opcodes and it is maximum number of opcodes, but the answer is given as c, which is 2^12 . How is this possible?

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    \$\begingroup\$ The question is asking how many DIFFERENT opcodes in the ISA, not how many instructions can make up the largest possible program. \$\endgroup\$
    – user16324
    Commented May 5, 2018 at 11:05
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    \$\begingroup\$ @BrianDrummond - with that interpretation, however, there question is only meaningful if you make assumptions about the way the ISA works that are not universal. E.g., the Z80 has an 8 bit data bus, but somewhere in the region of 800 different valid opcodes -- because it uses prefix bytes to extend and vary the available operations. \$\endgroup\$
    – Jules
    Commented May 5, 2018 at 20:24
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    \$\begingroup\$ The question as phrased in the book makes no sense. There's no inherent direct correspondence between bus size and opcode size. The JVM is based on a 32-bit data model but has 8-bit opcodes. \$\endgroup\$ Commented May 5, 2018 at 20:52
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    \$\begingroup\$ This question is incoherent unless we have a lot of information beyond what's given in the question. We'd have to make a lot of assumptions about the characteristics of the process to get an answer -- assumptions that are not true for the vast majority of real world processors! \$\endgroup\$ Commented May 5, 2018 at 22:27
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    \$\begingroup\$ The question is bullshit. If necessary, an instruction opcode can span multiple memory words. There is no inherent limit. \$\endgroup\$
    – Hot Licks
    Commented May 6, 2018 at 1:12

4 Answers 4


All options are wrong. Maximum number of (unique) opcodes a processor can execute is not limited by bus width.

One may think that a CPU with 12-bit data bus would probably be designed to be able to fit its instruction in a single data word so that it can read instructions in one go - because 2^12 = 4096 opcodes is more than enough for most purposes.

But, alongside opcodes, instructions may also contain arguments that often require an entire data word - so they wouldn't fit anyway - at this point it's not always useful to try to separate an opcode into its own word: some commands may pack 6-bit opcodes with 6 bits for arguments in one word, while others have one 12-bit opcode word plus several words of data. But then a CPU cannot have 2^12 instructions because it wouldn't be able to distinguish between the two instruction types.

On other hand, as pointed out in comments, some say that x86 has more than 6000 opcodes (although not all of them have unique function or are useful).

Yet another point is, for a 4-bit CPU though 2^4 = 16 instructions are very often not enough, so it has to have a way to fit more than that.

My point is that opcode count is limited by CPU instruction format, and not by bus width.

There can be multiple ways and reasons a CPU may incorporate more opcodes than what fits into the data bus, including:

Word-spanning instructions

A processor does not need to read a command in a single data cycle - it can use multiple consequential cycles. In fact most CPUs don't - although its more commonly used for instruction arguments rather then to expand opcode space.

Example: intel 4004 has only 4 lines which are multiplexed as data/address lines, 4-bit data word, but more than 40 opcodes in 8-bit instructions.

Prefixes and suffixes

A (CISC) processor may have as many instruction prefixes and suffixes as it needs.

Those are prefixed to an actual instruction to change what it does - either a little or completely.

It depends on your definition of "unique opcode". If one assumes any part of an instruction that is not data to be a part of opcode, their total number would include all possible variations. However, some believe those affixes are distinct parts of instruction.

Example: Intel x86 CPUs do not actually have 4M opcodes. However if you count all prefixes as a part of an opcode, modern CPUs allow for instructions as long as 15 bYtes - that's a LOT of possible opcodes. Although many will just do the same thing - so this depends on definition of them being "unique".


A processor may have multiple modes of operation in which it may have a completely different set of opcodes.

Examples: intel x86_64 has 32-bit (real/v86/protected) and 64-bit modes which have distinct opcodes. ARM CPUs can have ARM 32-bit and thumb 16-bit modes.

Bus bit multiplexing

The questions states "data lines" and "address lines", however both internal data bus and internal address bus may be wider than the amount of actual bus lines.

The multiplexed bus data is sent sequentially, i.e. first half, then second half. The CPU stores it into full-sized internal registers and operates on those.

This is often done to reduce costs and/or chip physical footprint size.

Examples include intel 4004, anything on LPC data bus, and NEC VR4300, Nintendo64's CPU that only had 32-line data bus.

No parallel bus

As a continuation of previous point, a CPU does not even need to expose a parallel bus at all.

A CPU may easily only expose a sequential bus such as I2C, SPI, etc.

It's probably not very cost-effective to produce such a dedicated CPU, but a lot of low-pin-count microcontrollers (that include both CPU and memory) are made that way to save those precious pins for something more useful. For example, atmel ATTINY4/5/6/10 chips only has 6 pins total, two for power, one for reset, three general-purpose. The instructions are sent via proprietary 3-line interface sequentially.

Depending on your definition of a microcontroller, it can be considered a microprocessor or can be programmed to act a one (i.e. simulate a dedicated CPU with a sequential bus or buses).

This question clearly states that some kind of data bus IS exposed, but not that it is a parallel bus. In theory the 12-line data bus could consist of a single serial data line and 11 auxilary/ground/status lines, although that probably wouldn't be a very sane idea.

Dedicated instruction bus

Actually a processor does not even need to accept instructions on the same bus lines as it does data.

This could easily be the case when ALUs were discrete chips rather than a part of a microprocessor but is not economically viable now most of the time.

But nothing prevents you from implementing a CPU with dedicated lines just for instructions. Such a CPU may be useful when a single operation must be done on an array of data (SIMD).

Since instruction bus width is completely arbitrary, so is maximum possible opcode count.

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    \$\begingroup\$ As a point of interest, x86-64 has between 1000 and 6000 opcodes, depending on who you ask (1, 2, 3). \$\endgroup\$
    – LMS
    Commented May 5, 2018 at 18:30
  • \$\begingroup\$ Never tried to even count them, but with all the variations it makes sense. \$\endgroup\$
    – Jack White
    Commented May 5, 2018 at 23:47

The maximum number of opcodes can indeed be thought of in a couple of ways:

  • The maximum possible number of unique opcodes.

This can be gathered from the instruction width and not the data bus width. Usually an opcode will fit into a single memory access, and then the answer is 2^12. But a processor could implement a multi-cycle opcode decoding process to extend the number of possible opcodes beyond 2^12.

  • The maximum number of instructions (containing opcodes) that the processor can directly address.

The maximum number of instructions (containing opcodes) that the processor can directly address is limited by the address bus width (2^16). Indirectly the processor could however be able to address more memory e.g. an opcode could facilitate a page-swap or a similar operation to fetch instructions from another source.

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    \$\begingroup\$ The question is not that ambiguous. If it was supposed to be interpreted as your second point, it would have been formulated as "the maximum number of instructions that can be stored/addressed/...". The word "opcode" makes it pretty clear it is about the instruction set, not the about adressable range. \$\endgroup\$
    – dim
    Commented May 5, 2018 at 11:26
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    \$\begingroup\$ +1 for mentioning that multi-word op-codes are quite possible, so the question is not a very good one. \$\endgroup\$ Commented May 5, 2018 at 11:45
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    \$\begingroup\$ Native english speakers often have a bias that make it hard for them to just understand the bare meaning of the words they use. When international english speakers read or hear it they may not get the second (intended) meaning. The same applies when a student learns a new expression - if the formulations are ambiguous it is easy to misunderstand. So I would guess that the student has learnt that each instruction contains an opcode part within it. Yes, I would say that is true. Really, the wording of question 01. is ambiguous. \$\endgroup\$
    – HKOB
    Commented May 5, 2018 at 11:53
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    \$\begingroup\$ @SpehroPefhany Yep, the question is undoubtedly ambiguous without further context. If the OP was taught that, whatever the instruction length, the opcode will be fetched in the first memory access, then the answer is (c), otherwise, it is unanswerable. The point is, did the OP give enough context in his EE.SE question, or did his teacher(s) give something for granted and formulated an ambiguous question? \$\endgroup\$ Commented May 5, 2018 at 12:05
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    \$\begingroup\$ @SpehroPefhany True :) But the English - perhaps to their mild annoyance - are also part of the International English world ( bbc.com/capital/story/… ) \$\endgroup\$
    – HKOB
    Commented May 5, 2018 at 12:36

You're right to be confused by this question - it's very badly written.

However, I suspect that the intent of this question is to determine the instruction word size for the machine. Given the very incomplete data provided, this must correspond to the width of the data bus; the width of the address bus determines the maximum size of the main memory.

In practice, the "opcode" field of a given machine's instructions is often significantly smaller than the instruction itself, yet the instruction may be wider than the data bus is.

The old Motorola 68008 is a case in point - it was a cost-reduced version of the 68000 with an 8-bit data bus, but it used the same 16-bit instruction words, in which typically 7 bits determine the opcode (the remainder identify the source and destination registers, and the addressing mode, all of which should be considered operands, not opcode). If you include the addressing mode bits in the opcode, as some do, that makes a 10-bit opcode field in total. The actual instructions could be substantially longer in some addressing modes.

  • \$\begingroup\$ "the remainder identify the source and destination registers, and the addressing mode, all of which should be considered operands, not opcode" ... well, that's a bit of a matter of opinion. For a RISC architecture, that's clearly true, but in many cases CISC architectures are defined in such an ad hoc way that it probably makes sense to count each combination as a separate opcode. The Z80 is a case in point - while many of its instructions have one or two register selections encoded in the bits of the opcode, the addressing modes are entirely ad-hoc and prefixes alter the interpretation of... \$\endgroup\$
    – Jules
    Commented May 6, 2018 at 12:06
  • \$\begingroup\$ ... both addressing mode and register in many cases, which makes interpretation of the registers from the bitfields a little less than straightforward. Most documentation and assemblers seem to work on the understanding, therefore, that each combination of instruction and registers is a separate opcode, and only immediate values and indirect address offset values are actually operands. This world view is shared by its predecessor, the intel 8080, where the standard assembly language format had registers operated on by an instruction encoded as part of the mnemonic, not given as arguments. \$\endgroup\$
    – Jules
    Commented May 6, 2018 at 12:09
  • \$\begingroup\$ True - the Z80 is typical of 8-bit microcoded CPUs that way. The 6502 had a more logical opcode mapping which allowed the decode circuitry to be optimised. But I was specifically talking about 68K, which has very distinct addressing-mode and destination-register fields in its instructions. After subtracting those, the opcode field can still be wider than the 68008's data bus. \$\endgroup\$
    – Chromatix
    Commented May 6, 2018 at 14:05

Edson DeCastro designed a computer almost exactly like that, the PDP-8, with 15 address and 12 data lines.

So the answer to the posted question is 574 op-codes, because the PDP-8 had 284 op-codes, and Ed is only half crazy.

  • 2
    \$\begingroup\$ Not sure why the downvote -- this is as good an answer as any, given that the question is essentially meaningless. :) \$\endgroup\$
    – Jules
    Commented May 6, 2018 at 12:11
  • \$\begingroup\$ I suspect the downvote is because 284*2=568, not 574. \$\endgroup\$
    – Mark
    Commented May 7, 2018 at 5:22

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