# Verilog reset example within clock domain crossing example

I'm trying to understand CDC problem and study some example with reference site. Currently, I'm referencing http://www.fpga4fun.com/CrossClockDomain2.html

Especially, I can't got any signals correctly working.

module Flag_CrossDomain(
input clkA,
input FlagIn_clkA,   // this is a one-clock pulse from the clkA domain
input clkB,
output FlagOut_clkB   // from which we generate a one-clock pulse in clkB domain
);

reg FlagToggle_clkA;
always @(posedge clkA) FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;  // when flag is asserted, this signal toggles (clkA domain)

reg [2:0] SyncA_clkB;
always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};  // now we cross the clock domains

assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);  // and create the clkB flag
endmodule


So, I just thought that that module missing reset. so I added it as the below. but not sure whether i do correctly modify or not. I mean that really do I need to reset signal?

module Flag_CrossDomain(
reset_n,
clkA,
FlagIn_clkA,
clkB,
FlagOut_clkB
);

input reset_n;
input clkA;
input FlagIn_clkA;
input clkB;
output   FlagOut_clkB ;

reg FlagToggle_clkA;
always @(posedge clkA or negedge reset_n)
if(!reset_n)
FlagToggle_clkA <= 0;
else
FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;

reg [2:0] SyncA_clkB;
always @(posedge clkB or negedge reset_n)
if(!reset_n)
SyncA_clkB <=0;
else
SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};

assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule


This code doesn't really need to be reset. If you do want to reset it, it has to be done properly, most likely with one reset signal for each clock domain. But this isn't really necessary, all you really need to do for simulation is initialize all the internal registers to something other than x, and then it should work properly. So, replace

reg FlagToggle_clkA;


with

reg FlagToggle_clkA = 0;


and you should be good to go.

• Possible but not recommended. See electronics.stackexchange.com/questions/352567/… Also not 100% correct, SyncA_clkB need to be reset too May 5, 2018 at 15:53
• They don't need to be reset so long as whatever they're connected to gets reset properly or can run without being reset. The only thing needed in this case is to make sure all of the X states can get flushed out, and the only thing preventing that is the initial value of FlagToggle_clkA. It doesn't matter if that starts at 0 or 1, only that it doesn't start at X. I actually try to only reset what is actually necessary to reset to simplify reset routing and improve timing performance and resource utilization. Haven't run in to any issues so far. May 5, 2018 at 15:59
• Wrong, without proper flushing and not knowing what SyncA_clkB is you can get false pulses at the output. May 5, 2018 at 16:02
• You do get false pulses, you just need to make sure to hold the reset of whatever is downstream until those have cleared out of the shift register. Resets should be filtered, extended, and synchronized into every clock domain anyway, so in a properly designed system this should not be a problem. May 5, 2018 at 16:09
• It's also entirely possible that the downstream logic doesn't care about a couple of false pulses. Depends on the application of the synchronizer. May 5, 2018 at 16:10

Without reset you registers all have an initial state of 1'bX. The code at the begin (without reset) will not work as 1'bX ^ SIGNAL produced 1'bX independent of the value of SIGNAL. Also you data shift SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA} will start as 3'bXXX and just shift X-es in. It thus it remain 3'bXXX.

With you reset your registers they all start at 0 and the system works.

• With a single async reset input, how do you ensure that there are no timing violations across the two clock domains upon releasing the reset? May 5, 2018 at 16:27