I have a piece of code that mainly consists of matrix-matrix and matrix-vector multiplications, but has other operations too. I have written my code in both Python and C and would like to map it to an Intel FPGA.
What I currently do is that I write a Verilog code that implements the same Python/C code and instantiates as many multipliers and adders as it is required to perform all operations in parallel. Obviously, this is not a scalable solution because when the size of matrices becomes large, all device resources will be exhausted quickly. As a result, there should be something like high-level synthesis that schedules these operations in different cycles.
Since I have not worked on such large designs before, I'm not sure what the best way is to go from a Python/C code to a code that includes the required datapath and controller for FPGA implementation.
Should I use a high-level synthesis tool that converts my C code to a Verilog code or there are better/easier solutions?