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Hello I am making a VHDL project in which I am doing some image processing. Color data of pixels are held in Rom and operations are done on Ram. However, when I try to reset the ram from the rom. It is not reset as intented. What I mean is that in place of what should have been the default picture on the moniter, there is a square which is consisting of just one color. When I reset the ram, what should happen is that I should see the default picture on the monitor but I cannot. I tried to debug code but could not see the fault. There could be some other problems in the code given below. How can I solve this problem?? Also I get this warning

  [Synth 8-6014] Unused sequential element address_rom_reg was removed.  

Here is what I have::

Reading_Writing_Resetting_Ram: process(clk,rst) is
begin
  if rst = '1' then 
    done <= '0';
  elsif rising_edge(clk) then
    if done = '0' then
      if address_rom < 
        conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then
        write_enable <= '1';
        data_in_ram <= data_rom;
        address_ram <= address_rom;
        address_rom <= address_rom + 1;
        if address_rom = 
          conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then
          address_rom <= (others => '0');
          write_enable <= '0';
          done <= '1';
        end if;
      end if;
    else --if done = '1'
      if (pos_x < PICTURE_WIDTH_HEIGHT)
      and (pos_y <PICTURE_WIDTH_HEIGHT)
      and (pos_x >= 0) and (pos_y >= 0) then -- if within picture
        address_ram <= (conv_std_logic_vector((pos_x + 
          pos_y*PICTURE_WIDTH_HEIGHT),16));
        if (pos_x > control_cursor_pos_x - 1)
        and (pos_x < control_cursor_pos_x + length)
        and (pos_y > control_cursor_pos_y - 1)
        and (pos_y < control_cursor_pos_y + length) then --if within cursor
          data_in_ram <= output_of_operation;
          if enable = '1' then
            write_enable <= '1';
          else
            write_enable <= '0';
          end if;
        end if;
      end if;
    end if;
  end if;
end process;

and

U3: Block_Rom port map(addra => address_rom,
                       clka => clk,
                       douta => data_rom);

U4: Block_Ram port map(addra => address_ram,
                       clka => clk,
                       dina => data_in_ram,
                       douta => data_out_ram,
                       wea => write_enable);

component Block_Rom
port(addra : in std_logic_vector(15 downto 0);
     clka : in std_logic;
     douta : out std_logic_vector(11 downto 0));

end component;

component Block_Ram
port(addra :in std_logic_vector(15 downto 0);
     clka : in std_logic;
     dina : in std_logic_vector(11 downto 0);
     douta: out std_logic_vector(11 downto 0);
     wea: in std_logic);
     end component;
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  • \$\begingroup\$ You say one concerning thing : you get a synth warning. Which leads to the question : did this work in simulation? If you haven't simulated it yet, stop what you're doing and write a testbench to exercise it, and simulate that. Otherwise, you're doing things the hard way. \$\endgroup\$ May 6 '18 at 13:28
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One thing is that if address_rom = conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then is never true at this point due to the nested if statements. You might wanna change your second if-statement into an else condition of the first one.

  if address_rom < 
        conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then
        write_enable <= '1';
        data_in_ram <= data_rom;
        address_ram <= address_rom;
        address_rom <= address_rom + 1;
       else
          address_rom <= (others => '0');
          write_enable <= '0';
          done <= '1';
      end if;

Is address_rom initialized somewhere? For more detailed help we might need your whole code...

Can you explain what the second part of your code does, if done = '1'?

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  • \$\begingroup\$ What can I do? do you think \$\endgroup\$ May 6 '18 at 11:26
  • \$\begingroup\$ An elsif statement instead? \$\endgroup\$
    – po.pe
    May 6 '18 at 11:28
  • \$\begingroup\$ Well spotted! By the way: that should have been picked up in a good test-bench. \$\endgroup\$
    – Oldfart
    May 6 '18 at 11:36
  • \$\begingroup\$ Humpawumpa can you please give more clue? I looked at the code and if I convert it into elsif, code does not seem logical at all to my eyes. Please give me a bit more help. I would really appreciate. \$\endgroup\$ May 6 '18 at 11:40
  • \$\begingroup\$ An else alone would do. You want to increment the counter till it reached the end, then stop. I still think you should set the address to zero in your reset section. Then set your your picture width and height to some manageable number and run a test till completion (which is reading the first frame out). \$\endgroup\$
    – Oldfart
    May 6 '18 at 11:48
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For a thorough analysis we would need all the code inclusive test-bench, ROM and RAM models and also the code that reads from the memory and makes the video signal.

The latter is important as you state that the memory initialisation is failing, but it could just as well be that your reading or display image code is faulty.

It is good practice to reset all registers. I have not yet spotted how you make sure that e.g. address_rom starts from zero.

Then there is this code around enable which enables writing to memory again. There is no clue as when or how this is controlled.

The warning that address_rom is removed is a bit of a worry. However it may be that address_rom is not needed as it is almost duplicated in address_ram. So maybe there is some logic which derives the signal from that. It is a good idea to start with that. Trace it down e.g. by looking into the synthesized netlist what is connected to the ROM address bus.

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