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I'm trying to understand how a DDR receive circuit works. I'm reading the MachXO2 Family Data Sheet, page 22:

http://www.latticesemi.com/view_document?document_id=38834

What I don't get is this: there are some flip-flops labeled D and some labeled D/L. What difference is the document trying to indicate by labeling some of them D and others D/L?

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  • \$\begingroup\$ It would be better if you would extract and show the section instead of letting us download a huge document with subsequent no idea where to look. \$\endgroup\$ – Oldfart May 6 '18 at 15:04
  • \$\begingroup\$ @Oldfart Well I did say page 22. Apart from that its cumbersome to screen capture part of a PDF and besides there are copyrights issues. \$\endgroup\$ – EnTaroAdun May 6 '18 at 15:45
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On the next page (2-19), they have a similar diagram, and the text describes the FF whose output is labeled Q0 thusly:

In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type register or latch.

So I would infer that in general, the label "D/L" denotes such a configurable FF.

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  • \$\begingroup\$ Good catch. Accepted. \$\endgroup\$ – EnTaroAdun May 6 '18 at 15:46

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