Hi I am using a single port ram which is constructed using block memory generator in Vivado. When I am reading its summery, something caught my eye. In summary it says total port a read latency: 2 clock cycle(s). What does that mean and how does it affect my operations??
\$\begingroup\$
\$\endgroup\$
Add a comment
|
2 Answers
\$\begingroup\$
\$\endgroup\$
There should be a diagram in the tool/data sheet of the RAMs that you chose and/or were used as reported in summary too. Typically you can choose, registered in and/or out or not, and maybe even choose how many delays(?)
\$\begingroup\$
\$\endgroup\$
4
It means it takes two clock cycles for the data to come out. However without more details I can't tell you two clocks after what. Probably after you present the read address and read enable.
-
\$\begingroup\$ There is no read enable. I think after I present the address new data comes out. It is very sad \$\endgroup\$ Commented May 6, 2018 at 19:35
-
\$\begingroup\$ If I understand right, I must use 100Mhz clock when reading data and I must use 25Mhz clock for VGA. By this way I can make things correct \$\endgroup\$ Commented May 6, 2018 at 19:41
-
\$\begingroup\$ sorry 50Mhz clock for Ram \$\endgroup\$ Commented May 6, 2018 at 19:48
-
\$\begingroup\$ I don't know what more there is in your system but normally there should be no problem. All the data comes out just a clock cycle later. But the video stream should be the same. \$\endgroup\$– OldfartCommented May 6, 2018 at 19:51